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ORCIDFernando Latorre
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2010 – 2019
- 2012
[c9]Demos Pavlou, Enric Gibert, Fernando Latorre, Antonio González
:
DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support. VEE 2012: 159-168- 2011
- [j2]Fernando Latorre, Grigorios Magklis, José González, Pedro Chaparro, Antonio González:
CROB: Implementing a Large Instruction Window through Compression. Trans. High Perform. Embed. Archit. Compil. 3: 115-134 (2011) - [c8]Rakesh Ranjan, Fernando Latorre, Pedro Marcuello, Antonio González:
Fg-STP: Fine-Grain Single Thread Partitioning on Multicores. HPCA 2011: 15-24 - 2010
- [b1]Antonio González, Fernando Latorre, Grigorios Magklis:
Processor Microarchitecture: An Implementation Perspective. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2010, ISBN 978-3-031-00601-2
2000 – 2009
- 2009
- [c7]Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González:
Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading. PACT 2009: 15-25 - [c6]Rakesh Ranjan, Pedro Marcuello, Fernando Latorre, Antonio González:
P-slice based efficient speculative multithreading. HiPC 2009: 119-128 - [c5]Carlos Madriles, Pedro López, Josep M. Codina, Enric Gibert, Fernando Latorre, Alejandro Martínez, Raúl Martínez, Antonio González:
Boosting single-thread performance in multi-core systems through fine-grain multi-threading. ISCA 2009: 474-483 - 2008
- [c4]Fernando Latorre, José González, Antonio González:
Efficient resources assignment schemes for clustered multithreaded processors. IPDPS 2008: 1-12 - 2007
- [c3]Fernando Latorre, Grigorios Magklis, José González, Pedro Chaparro, Antonio González:
Building a large instruction window through ROB compression. MEDEA@PACT 2007: 41-48 - 2004
- [c2]Fernando Latorre, José González, Antonio González:
Back-end assignment schemes for clustered multithreaded processors. ICS 2004: 316-325 - [c1]José González, Fernando Latorre, Antonio González:
Cache organizations for clustered microarchitectures. WMPI 2004: 46-55 - 2002
- [j1]Rajagopalan Desikan, Doug Burger, Stephen W. Keckler, José-Lorenzo Cruz, Fernando Latorre, Antonio González, Mateo Valero:
Errata on "Measuring Experimental Error in Microprocessor Simulation". SIGARCH Comput. Archit. News 30(1): 2-4 (2002)
Coauthor Index
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