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ORCIDJeffrey H. Dreibelbis
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- affiliation: IBM Systems and Technology Group, Essex Junction, VT, USA
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2000 – 2009
- 2007
[c5]Darren Anand, Jim Covino, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Mark Jacunski, Jake Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva:
A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST. CICC 2007: 795-798- 2005
- [j4]John E. Barth Jr., Darren Anand, Steve Burns, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Michael R. Nelms, Erik Nelson, Adrian Paparelli
, Gary Pomichter, Dale E. Pontius, Stephen Sliva:
A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. IEEE J. Solid State Circuits 40(1): 213-222 (2005) - 2002
- [j3]John E. Barth Jr., Jeffrey H. Dreibelbis, Eric A. Nelson, Darren Anand, Gary Pomichter, Peter Jakobsen, Michael R. Nelms, Jeffrey Leach, George M. Belansek:
Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering. IBM J. Res. Dev. 46(6): 675-690 (2002) - 2001
- [c4]Roderick McConnell, Rochit Rajsuman, Eric A. Nelson, Jeffrey H. Dreibelbis:
Test and repair of large embedded DRAMs. I. ITC 2001: 163-172 - [c3]Eric A. Nelson, Jeffrey H. Dreibelbis, Roderick McConnell:
Test and repair of large embedded DRAMs. 2. ITC 2001: 173-181 - [c2]Peter Jakobsen, Jeffrey H. Dreibelbis, Gary Pomichter, Darren Anand, John Barth, Michael R. Nelms, Jeffrey Leach, George M. Belansek:
Embedded DRAM built in self test and methodology for test insertion. ITC 2001: 975-984 - [c1]Brian R. Kessler, Jeffrey H. Dreibelbis, Tim McMahon, Joshua S. McCloy, Rex Kho:
BIST-Based Bitfail Mapping of an Embedded DRAM. MTDT 2001: 29-
1990 – 1999
- 1998
- [j2]Jeffrey H. Dreibelbis, John Barth, Howard L. Kalter, Rex Kho:
Processor-based built-in self-test for embedded DRAM. IEEE J. Solid State Circuits 33(11): 1731-1740 (1998) - 1995
- [j1]Wayne F. Ellis, John E. Barth Jr., Sri Divakaruni, Jeffrey H. Dreibelbis, Anatol Furman, Erik L. Hedberg, Hsing-San Lee, Thomas M. Maffitt, Christopher P. Miller, Charles H. Stapper, Howard L. Kalter:
Multipurpose DRAM architecture for optimal power, performance, and product flexibility. IBM J. Res. Dev. 39(1-2): 51-62 (1995)
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