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2020 – today
- 2021
[j14]Cheonyong Kim
, Joobum Kim, Ki-Hyeon Kim, Sang-Kwon Lee, Ki-Wook Kim, Syed Asif Raza Shah, Young-Hoon Goo:
ScienceIoT: Evolution of the Wireless Infrastructure of KREONET. Sensors 21(17): 5852 (2021)
2010 – 2019
- 2018
- [j13]Ki-Wook Kim, Sung-Gi Min, Youn-Hee Han:
In-Network Data Processing in Software-Defined IoT with a Programmable Data Plane. Mob. Inf. Syst. 2018: 8618267:1-8618267:9 (2018) - 2017
- [j12]Ki-Wook Kim, Youn-Hee Han, Sung-Gi Min:
An Authentication and Key Management Mechanism for Resource Constrained Devices in IEEE 802.11-based IoT Access Networks. Sensors 17(10): 2170 (2017) - [c19]Ki-Wook Kim, Sung-Gi Min, Youn-Hee Han:
A programmable data plane to support in-network data processing in software-defined IoT. ICTC 2017: 855-860
2000 – 2009
- 2009
- [c18]Ki-Wook Kim, Kwang-Ryoul Kim, Sung-Gi Min:
Distributed cluster head election algorithm using local energy estimation. ICHIT 2009: 256-259 - 2004
- [j11]Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim:
Coupling-aware high-level interconnect synthesis [IC layout]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 157-164 (2004) - 2003
- [j10]Jaesik Lee, Ki-Wook Kim, Yoonjong Huh, Peter Bendix, Sung-Mo Kang:
Chip-level charged-device modeling and simulation in CMOS integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 67-81 (2003) - [j9]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Timing constraints for domino logic gates with timing-dependent keepers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 96-103 (2003) - [j8]Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang:
Minimum delay optimization for domino circuits - a coupling-aware approach. ACM Trans. Design Autom. Electr. Syst. 8(2): 202-213 (2003) - [j7]Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang:
Energy-efficient skewed static logic with dual Vt: design and synthesis. IEEE Trans. Very Large Scale Integr. Syst. 11(1): 64-70 (2003) - [j6]Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang:
Noise-aware interconnect power optimization in domino logic synthesis. IEEE Trans. Very Large Scale Integr. Syst. 11(1): 79-89 (2003) - [j5]Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang:
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 879-887 (2003) - 2002
- [j4]Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang:
Domino logic synthesis based on implication graph. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2): 232-240 (2002) - [j3]Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu:
Logic transformation for low-power synthesis. ACM Trans. Design Autom. Electr. Syst. 7(2): 265-283 (2002) - [j2]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Noise constrained transistor sizing and power optimization for dual Vst domino logic. IEEE Trans. Very Large Scale Integr. Syst. 10(5): 532-541 (2002) - [c17]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Low-swing clock domino logic incorporating dual supply and dual threshold voltages. DAC 2002: 467-472 - [c16]Jaesik Lee, Ki-Wook Kim, Sung-Mo Kang:
VeriCDF: a new verification methodology for charged device failures. DAC 2002: 874-879 - [c15]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain. DATE 2002: 260-265 - [c14]Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim:
Coupling-aware high-level interconnect synthesis for low power. ICCAD 2002: 609-613 - [c13]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Optimal Timing for Skew-Tolerant High-Speed Domino Logic. ISVLSI 2002: 41-46 - 2001
- [b1]Ki-Wook Kim:
Reliable Low -Power Solution for High -Performance VLSI Circuit Design. University of Illinois Urbana-Champaign, USA, 2001 - [j1]Ki-Wook Kim, Sung-Mo Kang:
Crosstalk noise minimization in domino logic design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9): 1091-1100 (2001) - [c12]Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang:
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. DAC 2001: 732-737 - [c11]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Transistor sizing for reliable domino logic design in dual threshold voltage technologies. ACM Great Lakes Symposium on VLSI 2001: 133-138 - [c10]Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang:
Skew-tolerant high-speed (STHS) domino logic. ISCAS (4) 2001: 154-157 - [c9]Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Noise constrained power optimization for dual VT domino logic. ISCAS (4) 2001: 158-161 - [c8]Ki-Wook Kim, Seong-Ook Jung, Sung-Mo Kang:
Coupling-aware minimum delay optimization for domino logic circuits. ISCAS (5) 2001: 371-374 - [c7]Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang:
Energy-efficient skewed static logic design with dual Vt. ISCAS (4) 2001: 882-885 - 2000
- [c6]Ki-Wook Kim, Unni Narayanan, Sung-Mo Kang:
Domino logic synthesis minimizing crosstalk. DAC 2000: 280-285 - [c5]Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang:
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. ICCAD 2000: 318-321 - [c4]Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang:
Noise-aware power optimization for on-chip interconnect. ISLPED 2000: 108-113
1990 – 1999
- 1999
- [c3]Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu:
Logic Transformation for Low Power Synthesis. DATE 1999: 158-162 - [c2]Ki-Wook Kim, C. L. Liu, Sung-Mo Kang:
Implication graph based domino logic synthesis. ICCAD 1999: 111-114 - 1996
- [c1]Ki-Wook Kim, Ki-Byoung Kim, Hyoung-Joo Kim:
VIRON: An Annotation-Based Video Information Retrieval System. COMPSAC 1996: 298-303
Coauthor Index
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