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ORCIDIan G. Harris
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- affiliation: University of California, Irvine, USA
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2020 – today
- 2024
[i5]Yurun Song, Junchen Zhao, Ian G. Harris, Sangeetha Abdu Jyothi:
ShareLoRA: Parameter Efficient and Robust Large Language Model Fine-tuning via Shared Low-Rank Adaptation. CoRR abs/2406.10785 (2024)- 2023
- [c65]Junchen Zhao, Yurun Song, Junlin Wang, Ian G. Harris:
GAP-Gen: Guided Automatic Python Code Generation. EACL (Student Research Workshop) 2023: 37-51 - [c64]Yurun Song, Junchen Zhao, Spencer Koehler, Amir Abdullah, Ian G. Harris:
PCMID: Multi-Intent Detection through Supervised Prototypical Contrastive Learning. EMNLP (Findings) 2023: 9481-9495 - [c63]Jie Wu, Ian G. Harris, Hongzhi Zhao, Guangming Ling:
A Graph-to-Sequence Model for Joint Intent Detection and Slot Filling. ICSC 2023: 131-138 - [i4]Dongyu Yao, Jianshu Zhang, Ian G. Harris, Marcel Carlsson:
FuzzLLM: A Novel and Universal Fuzzing Framework for Proactively Discovering Jailbreak Vulnerabilities in Large Language Models. CoRR abs/2309.05274 (2023) - [i3]Jinhwa Kim, Ali Derakhshan, Ian G. Harris:
Robust Safety Classifier for Large Language Models: Adversarial Prompt Shield. CoRR abs/2311.00172 (2023) - [i2]Junchen Zhao, Yurun Song, Simeng Liu, Ian G. Harris, Sangeetha Abdu Jyothi:
LinguaLinked: A Distributed Large Language Model Inference System for Mobile Devices. CoRR abs/2312.00388 (2023) - 2022
- [c62]Jie Wu, Ian G. Harris, Hongzhi Zhao:
GraphMemDialog: Optimizing End-to-End Task-Oriented Dialog Systems Using Graph Memory Networks. AAAI 2022: 11504-11512 - [c61]Mitra Behzadi, Ali Derakhshan, Ian G. Harris:
Mitra Behzadi at SemEval-2022 Task 5 : Multimedia Automatic Misogyny Identification method based on CLIP. SemEval@NAACL 2022: 724-727 - [i1]Junchen Zhao, Yurun Song, Junlin Wang, Ian G. Harris:
GAP-Gen: Guided Automatic Python Code Generation. CoRR abs/2201.08810 (2022) - 2021
- [c60]Ali Derakhshan, Ian G. Harris, Mitra Behzadi:
Detecting Telephone-based Social Engineering Attacks using Scam Signatures. IWSPA@CODASPY 2021: 67-73 - [c59]Yu-Jye Tung, Ian G. Harris:
Zero Footprint Opaque Predicates: Synthesizing Opaque Predicates from Naturally Occurring Invariants. DIMVA 2021: 299-318 - [c58]Jie Wu, Ian G. Harris, Hongzhi Zhao:
Spoken Language Understanding for Task-oriented Dialogue Systems with Augmented Memory Networks. NAACL-HLT 2021: 797-806 - [c57]Mitra Behzadi, Ian G. Harris, Ali Derakhshan:
Rapid Cyber-bullying detection method using Compact BERT Models. ICSC 2021: 199-202 - 2020
- [c56]Jinhwa Kim, Yoon Jo Kim, Mitra Behzadi, Ian G. Harris:
Analysis of Online Conversations to Detect Cyberpredators Using Recurrent Neural Networks. STOC@LREC 2020: 15-20 - [c55]Ian G. Harris, Ali Derakhshan, Marcel Carlsson:
A Study of Targeted Telephone Scams Involving Live Attackers. STAST 2020: 63-82
2010 – 2019
- 2019
- [c54]Junchen Zhao, Ian G. Harris:
Automatic Assertion Generation from Natural Language Specifications Using Subtree Analysis. DATE 2019: 598-601 - [c53]Oliver Keszöcze
, Ian G. Harris:
Chatbot-based assertion generation from natural language specifications. FDL 2019: 1-6 - [c52]Myeongsoo Kim, Changheon Song, Hyeji Kim, Deahyun Park, Yeeji Kwon, Eun Namkung, Ian G. Harris, Marcel Carlsson:
Scam Detection Assistant: Automated Protection from Scammers. SA 2019: 1-8 - 2018
- [c51]Tianrui Peng, Ian G. Harris, Yuki Sawa:
Detecting Phishing Attacks Using Natural Language Processing and Machine Learning. ICSC 2018: 300-301 - 2017
- [c50]Sophia Balkovski, Ian G. Harris:
Designing cyber-physical systems from natural language descriptions. HLDVT 2017: 39-44 - [c49]Zonglin Guo, Ian G. Harris, Yutong Jiang, Lih-feng Tsaur:
An efficient approach to prevent Battery Exhaustion Attack on BLE-based mesh networks. ICNC 2017: 1-5 - 2016
- [c48]Christopher B. Harris, Ian G. Harris:
GLAsT: Learning formal grammars to translate natural language specifications into hardware assertions. DATE 2016: 966-971 - [c47]Sandip Ray, Ian G. Harris, Görschwin Fey, Mathias Soeken:
Multilevel design understanding: from specification to logic (invited paper). ICCAD 2016: 133 - [c46]Yuki Sawa, Ram Bhakta, Ian G. Harris, Christopher Hadnagy:
Detection of Social Engineering Attacks Through Natural Language Processing of Conversations. ICSC 2016: 262-265 - [c45]Zonglin Guo, Ian G. Harris, Christopher B. Harris, Yutong Jiang, Lih-feng Tsaur:
A residual battery-aware routing algorithm based on DSR for BLE sensor networks. WTS 2016: 1-6 - 2015
- [c44]Christopher B. Harris, Ian G. Harris:
Generating formal hardware verification properties from Natural Language documentation. ICSC 2015: 49-56 - [c43]Ram Bhakta, Ian G. Harris:
Semantic analysis of dialogs to detect social engineering attacks. ICSC 2015: 424-427 - [c42]Zonglin Guo, Ian G. Harris, Lih-feng Tsaur, Xianbo Chen:
An on-demand scatternet formation and multi-hop routing protocol for BLE-based wireless sensor networks. WCNC 2015: 1590-1595 - 2014
- [c41]Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, Ian G. Harris, Rolf Drechsler:
Automating the translation of assertions using natural language processing techniques. FDL 2014: 1-8 - [c40]Zonglin Guo, Ram Bhakta, Ian G. Harris:
Control-flow checking for intrusion detection via a real-time debug interface. SMARTCOMP Workshops 2014: 87-92 - 2013
- [c39]Dave W. Binkley, Dawn J. Lawrie, Emily Hill, Janet E. Burge, Ian G. Harris, Regina Hebig, Oliver Keszöcze, Karl Reed, John Slankas:
Task-Driven Software Summarization. ICSM 2013: 432-435 - 2012
- [j13]Mehryar Rahmatian, Hessam Kooti, Ian G. Harris, Elaheh Bozorgzadeh:
Hardware-Assisted Detection of Malicious Software in Embedded Systems. IEEE Embed. Syst. Lett. 4(4): 94-97 (2012) - [c38]Ian G. Harris:
Extracting design information from natural language specifications. DAC 2012: 1256-1257 - [c37]Mehryar Rahmatian, Hessam Kooti, Ian G. Harris, Elaheh Bozorgzadeh:
Minimization of Trojan footprint by reducing Delay/Area impact. DFT 2012: 59-62 - [c36]Ian G. Harris:
Automatic generation of Verilog bus transactors from natural language protocol specifications. HLDVT 2012: 33-40 - [c35]Rolf Drechsler, Ian G. Harris, Robert Wille:
Generating formal system models from natural language descriptions. HLDVT 2012: 164-165 - [c34]Mehryar Rahmatian, Hessam Kooti, Ian G. Harris, Elaheh Bozorgzadeh:
Adaptable intrusion detection using partial runtime reconfiguration. ICCD 2012: 147-152 - [c33]Patricia S. Lee, Ian G. Harris:
Test generation for subtractive specification errors. VTS 2012: 258-263 - 2011
- [e1]Sharon Barner, Ian G. Harris, Daniel Kroening, Orna Raz:
Hardware and Software: Verification and Testing - 6th International Haifa Verification Conference, HVC 2010, Haifa, Israel, October 4-7, 2010. Revised Selected Papers. Lecture Notes in Computer Science 6504, Springer 2011, ISBN 978-3-642-19582-2 [contents]
2000 – 2009
- 2009
- [j12]Ian G. Harris, Thoulfekar Alrahem, Alex Chen, Nicholas DiGiuseppe, Jefferey Gee, Shang-Pin Hsiao, Sean Mattox, Taejoon Park, Saravanan Selvaraj, Albert Tam, Marcel Carlsson:
Security testing of session initiation protocol implementations. ISC Int. J. Inf. Secur. 1(2): 91-103 (2009) - 2008
- [c32]Kiran Ramineni, Shireesh Verma, Ian G. Harris:
Evaluation of an efficient control-oriented coverage metric. HLDVT 2008: 153-157 - 2007
- [c31]Shireesh Verma, Ian G. Harris, Kiran Ramineni:
Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions. DATE 2007: 900-905 - [c30]Kiran Ramineni, Ian G. Harris, Shireesh Verma:
Improving feasible interactions among multiple processes. HLDVT 2007: 11-18 - [c29]Shireesh Verma, Ian G. Harris, Kiran Ramineni:
Automatic generation of functional coverage models from CTL. HLDVT 2007: 159-164 - [c28]Franco Fummi, Cristina Marconcini, Graziano Pravadelli, Ian G. Harris:
A CLP-Based Functional ATPG for Extended FSMs. MTV 2007: 98-105 - 2006
- [j11]Ian G. Harris, Franco Fummi:
Guest Editor's Introduction. Int. J. Parallel Program. 34(1): 1-2 (2006) - [j10]Ian G. Harris:
Guest Editor's Introduction to the Special Section on Simulation-Based Design Validation. IEEE Trans. Computers 55(11): 1313-1314 (2006) - [c27]Ian G. Harris:
A coverage metric for the validation of interacting processes. DATE 2006: 1019-1024 - [c26]Shireesh Verma, Patricia S. Lee, Ian G. Harris:
Error Detection Using Model Checking vs. Simulation. HLDVT 2006: 55-58 - 2005
- [j9]Franco Fummi, Ian G. Harris:
Editorial. Int. J. Parallel Program. 33(6): 583-584 (2005) - [j8]Matthew W. Heath, Wayne P. Burleson, Ian G. Harris:
Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test. IEEE Trans. Computers 54(12): 1532-1546 (2005) - [j7]Ian G. Harris:
Introduction. ACM Trans. Design Autom. Electr. Syst. 10(4): 587-588 (2005) - [c25]Shireesh Verma, Kiran Ramineni, Ian G. Harris:
An efficient control-oriented coverage metric. ASP-DAC 2005: 317-322 - [c24]Fei Xin, Maciej J. Ciesielski, Ian G. Harris:
Design validation of behavioral VHDL descriptions for arbitrary fault models. ETS 2005: 156-161 - 2004
- [j6]Carol Stolicny, Tapio Koivukangas, Rubin A. Parekhji, Ian G. Harris, Rob Aitken:
ITC 2003 panels: Part 1. IEEE Des. Test Comput. 21(2): 160-163 (2004) - [c23]Matthew W. Heath, Wayne P. Burleson, Ian G. Harris:
Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s. DATE 2004: 410-415 - 2003
- [j5]Ian G. Harris:
Fault Models and Test Generation for Hardware-Software Covalidation. IEEE Des. Test Comput. 20(4): 40-47 (2003) - [j4]Srikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris:
ATPG for Timing Errors in Globally Asynchronous Locally Synchronous Systems. J. Circuits Syst. Comput. 12(3): 305-332 (2003) - [j3]Qiushuang Zhang, Ian G. Harris:
Partial BIST insertion to eliminate data correlation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 374-379 (2003) - [c22]Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski:
Fast Computation of Data Correlation Using BDDs. DATE 2003: 10122-10129 - [c21]Emilio Gaudette, Michael Moussa, Ian G. Harris:
A method for the evaluation of behavioral fault models. HLDVT 2003: 169-172 - [c20]Dereck A. Fernandes, Ian G. Harris:
Application of Built in Self-Test for Interconnect Testing of FPGAs. ITC 2003: 1248-1257 - [c19]Ian G. Harris:
The Confluence of Manufacturing Test and Design Validation. ITC 2003: 1290 - [c18]Matthew W. Heath, Ian G. Harris:
A Deterministic Globally Asynchronous Locally Synchronousy Microprocessor Architecture. MTV 2003: 119- - 2002
- [j2]Ian G. Harris, Russell Tessier:
Testing and diagnosis of interconnect faults in cluster-based FPGA architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11): 1337-1343 (2002) - [c17]Srikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris:
ATPG for timing-induced functional errors on trigger events in hardware-software systems. ETW 2002: 23-28 - [c16]Fei Xin, Ian G. Harris:
Test generation for hardware-software covalidation using non-linear programming. HLDVT 2002: 175-180 - 2001
- [c15]Srikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris:
Test pattern generation for timing-induced functional errors in hardware-software systems. HLDVT 2001: 83-88 - [c14]Ian G. Harris:
Hardware-software covalidation: fault models and test generation. HLDVT 2001: 151-156 - [c13]Qiushuang Zhang, Ian G. Harris:
A validation fault model for timing-induced functional errors. ITC 2001: 813-820 - [c12]Ian G. Harris, Premachandran R. Menon, Russell Tessier:
BIST-based delay path testing in FPGA architectures. ITC 2001: 932-938 - 2000
- [c11]Ian G. Harris, Russell Tessier:
Interconnect testing in cluster-based FPGA architectures. DAC 2000: 49-54 - [c10]Qiushuang Zhang, Ian G. Harris:
A Data Flow Fault Coverage Metric for Validation of Behavioral HDL Descriptions. ICCAD 2000: 369-372 - [c9]Ian G. Harris, Russell Tessier:
Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures. ICCAD 2000: 472-475 - [c8]Qiushuang Zhang, Ian G. Harris:
A domain coverage metric for the validation of behavioral VHDL descriptions. ITC 2000: 302-308
1990 – 1999
- 1999
- [c7]Qiushuang Zhang, Ian G. Harris:
Partial BIST insertion to eliminate data correlation. ICCAD 1999: 395-399 - 1997
- [j1]Ian G. Harris, Alex Orailoglu:
Module Selection in Microarchitectural Synthesis for Multiple Critical Constraint Satisfaction. VLSI Design 5(2): 167-182 (1997) - 1994
- [c6]Ian G. Harris, Alex Orailoglu:
Microarchitectural Synthesis of VLSI Designs with High Test Concurrency. DAC 1994: 206-211 - [c5]Ian G. Harris, Alex Orailoglu:
Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST. EDAC-ETC-EUROASIC 1994: 119-123 - [c4]Ian G. Harris, Alex Orailoglu:
SYNCBIST: SYNthesis for Concurrent Built-In-Self-Testability. ICCD 1994: 101-104 - 1993
- [c3]Alex Orailoglu, Ian G. Harris:
Test Path Generation and Test Scheduling for Self-Testable Designs. ICCD 1993: 528-531 - [c2]Ian G. Harris, Alex Orailoglu:
Intertwined Scheduling, Module Selection and Allocation in Time-and-Area. ISCAS 1993: 1682-1685 - 1991
- [c1]P. Venkat Rangan, Walter A. Burkhard, Robert W. Rowdidge, Harrick M. Vin, John W. Lindwall, Kashun Chan, Ingvar A. Aaberg, Linda M. Yamamoto, Ian G. Harris:
A Testbed for Managing Digital Video and Audio Storage. USENIX Summer 1991: 199-208
Coauthor Index
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