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ORCIDAsim J. Al-Khalili
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- affiliation: Concordia University, Montreal, Canada
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2020 – today
- 2021
[j22]P. R. Berthelson
, Payam Ghassemi, J. W. Wood, G. G. Stubblefield, Asim J. Al-Khalili, M. D. Jones, Mark F. Horstemeyer, Souma Chowdhury, R. K. Prabhu:
A finite element-guided mathematical surrogate modeling approach for assessing occupant injury trends across variations in simplified vehicular impact conditions. Medical Biol. Eng. Comput. 59(5): 1065-1079 (2021)
2010 – 2019
- 2015
- [p1]Houman Zarrabi, A. J. Al-Khalili, Yvon Savaria:
Design Intelligence for Interconnection Realization in Power-Managed SoCs. Computational Intelligence in Digital and Network Designs and Applications 2015: 69-96 - 2014
- [c44]Seyed Ebrahim Esmaeili, Asim J. Al-Khalili:
10 GHz throughput FinFET dual-edge triggered flip-flops. CCECE 2014: 1-4 - [c43]Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria:
Vt-conscious repeater insertion in power-managed VLSI. ISIC 2014: 99-102 - 2013
- [j21]Seyed Ebrahim Esmaeili, Asim J. Al-Khalili:
Integrated Power and Clock Distribution Network. IEEE Trans. Very Large Scale Integr. Syst. 21(10): 1941-1945 (2013) - 2012
- [j20]Ali Valaee, A. J. Al-Khalili:
High-performance low-power sensing scheme for nanoscale SRAMs. IET Comput. Digit. Tech. 6(6): 406-413 (2012) - [j19]Afshin Nourivand, Asim J. Al-Khalili, Yvon Savaria:
Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 29-41 (2012) - [j18]Seyed Ebrahim Esmaeili, Asim J. Al-Khalili, Glenn E. R. Cowan:
Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1547-1551 (2012) - [c42]Seyed Ebrahim Esmaeili, Ali M. Farhangi, Asim J. Al-Khalili, Glenn E. R. Cowan:
Clock tree structure with reduced wire length using the matched-delay skew compensation technique. CCECE 2012: 1-4 - [c41]Seyed Ebrahim Esmaeili, Riadul Islam, Asim J. Al-Khalili, Glenn E. R. Cowan:
Dual-edge triggered sense amplifier flip-flop utilizing an improved scheme to reduce area, power, and complexity. ICECS 2012: 292-295 - 2011
- [j17]Afshin Nourivand, Asim J. Al-Khalili, Yvon Savaria:
Analysis of Resistive Open Defects in Drowsy SRAM Cells. J. Electron. Test. 27(2): 203-213 (2011) - [c40]Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria:
Repeater insertion in power-managed VLSI systems. ACM Great Lakes Symposium on VLSI 2011: 395-398 - [c39]Houman Zarrabi, A. J. Al-Khalili, Yvon Savaria:
Activity management in battery-powered embedded systems: A case study of ZigBee® WSN. ICECS 2011: 727-731 - [c38]Ali Valaee, Asim J. Al-Khalili:
SRAM read-assist scheme for high performanc low power applications. ISOCC 2011: 179-182 - 2010
- [j16]Seyed Ebrahim Esmaeili, Ali M. Farhangi, Asim J. Al-Khalili, Glenn E. R. Cowan:
Skew compensation in energy recovery clock distribution networks. IET Comput. Digit. Tech. 4(1): 56-72 (2010) - [j15]Seyed Ebrahim Esmaeili, A. J. Al-Khalili, Glenn E. R. Cowan:
Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks. IET Comput. Digit. Tech. 4(6): 499-514 (2010) - [c37]Seyed Ebrahim Esmaeili, Asim J. Al-Khalili, Glenn E. R. Cowan:
Estimating required driver strength in the resonant clock generator. APCCAS 2010: 927-930 - [c36]Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria:
An interconnect-aware Dynamic Voltage Scaling scheme for DSM VLSI. ISCAS 2010: 41-44 - [c35]Ali M. Farhangi, Asim J. Al-Khalili, Dhamin Al-Khalili:
Pattern-Driven Clock Tree Routing with Via Minimization. ISVLSI 2010: 216-221
2000 – 2009
- 2009
- [c34]Seyed Ebrahim Esmaeili, A. J. Al-Khalili, Glenn E. R. Cowan:
Dual-edge triggered energy recovery DCCER flip-flop for low energy applications. ECCTD 2009: 57-60 - [c33]Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria:
An interconnect-aware delay model for dynamic voltage scaling in NM technologies. ACM Great Lakes Symposium on VLSI 2009: 45-50 - [c32]Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria:
Estimation of energy performance in computing platforms. ICECS 2009: 783-786 - 2008
- [c31]Jacques Laurent Athow, Asim Jawad Al-Khalili:
Implementation of large-integer hardware multiplier in Xilinx FPGA. ICECS 2008: 1300-1303 - 2006
- [c30]A. J. Al-Khalili:
A CAD Tool for Scalable, Variable Architecture Floating-Point Adder Generator. AICCSA 2006: 74-79 - [c29]Asim J. Al-Khalili:
A CAD Tool for Generation of Synthesizable and Scalable Square of Binary Numbers. ICN/ICONS/MCL 2006: 183 - [c28]Houman Zarrabi, Haydar Saaied, Asim J. Al-Khalili, Yvon Savaria:
Zero skew differential clock distribution network. ISCAS 2006 - 2005
- [j14]Adnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili:
Delay analysis of CMOS gates using modified logical effort model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(6): 937-947 (2005) - [j13]Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili:
Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(10): 1637-1643 (2005) - [c27]Shaoqiang Bi, Warren J. Gross, Wei Wang, Asim J. Al-Khalili, M. N. S. Swamy:
An Area-Reduced Scheme for Modulo 2n-1 Addition/Subtraction. IWSOC 2005: 396-399 - 2004
- [c26]Shaoqiang Bi, Wei Wang, Asim J. Al-Khalili:
New modulo decomposed residue-to-binary algorithm for general moduli sets. ICASSP (5) 2004: 141-144 - [c25]Shaoqiang Bi, Wei Wang, Asim J. Al-Khalili:
Modulo deflation in (2n+1, 2n, 2n-1) converters. ISCAS (2) 2004: 429-432 - [c24]Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili:
Clock tree tuning using shortest paths polygon. SoCC 2004: 59-62 - 2003
- [j12]Adnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili:
Technology-portable analytical model for DSM CMOS inverter transition-time estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(9): 1177-1187 (2003) - [j11]Cheng-Yu Pai, Asim J. Al-Khalili, William E. Lynch:
Low-Power Constant-Coefficient Multiplier Generator. J. VLSI Signal Process. 35(2): 187-194 (2003) - [c23]Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili:
Adaptive wire adjustment for bounded skew Clock Distribution Network. ASP-DAC 2003: 243-248 - [c22]Asim J. Al-Khalili, Aiping Hu:
Design of a 32-bit squarer - exploiting addition redundancy. ISCAS (5) 2003: 325-328 - 2002
- [c21]Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili:
Quadratic deferred-merge embedding algorithm for zero skew clock distribution network. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 119-125 - 2001
- [j10]R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili, S. Y. A. Shah:
A Low Power Approach to Floating Point Adder Design for DSP Applications. J. VLSI Signal Process. 27(3): 195-213 (2001) - [c20]R. V. K. Pillai, S. Y. A. Shah, A. J. Al-Khalili, Dhamin Al-Khalili:
Low power floating point MAFs-a comparative study. ISSPA 2001: 284-287 - 2000
- [c19]P. Sun, A. J. Al-Khalili, Dhamin Al-Khalili:
A CAD tool for first hand CMOS circuit selection. ICECS 2000: 165-168
1990 – 1999
- 1999
- [c18]R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili:
An IEEE Compliant Floating Point MAF. VLSI 1999: 149-160 - [c17]R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili:
Power implications of precision limited arithmetic in floating point FIR filters. ISCAS (1) 1999: 165-168 - [c16]Adnan Kabbani, A. J. Al-Khalili:
Dynamic CMOS noise immunity estimation in submicron regime. ISCAS (1) 1999: 529-532 - [c15]Adnan Kabbani, A. J. Al-Khalili:
Estimation of ground bounce effects on CMOS circuits. ISCAS (1) 1999: 533-536 - [c14]Jacob Augustine, William E. Lynch, Yuke Wang, Asim J. Al-Khalili:
Lossy Compression of Images Using Logic Minimization. VLSI Design 1999: 538-543 - 1998
- [c13]R. V. K. Pillai, Asim J. Al-Khalili, Dhamin Al-Khalili:
A Low Power Floating Point Accumulator. VLSI Design 1998: 330- - 1997
- [c12]R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili:
A Low Power Approach to Floating Point Adder Design. ICCD 1997: 178-185 - [c11]R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili:
Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition. ISLPED 1997: 235-238 - 1996
- [c10]H. Ahmad, Asim J. Al-Khalili, L. Landsberger, M. Kahrizi:
A 2D micromachined accelerometer. ICECS 1996: 908-911 - [c9]R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili:
Energy delay analysis of partial product reduction methods for parallel multiplier implementation. ISLPED 1996: 201-204 - 1995
- [j9]Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri:
Area efficient computing structures for concurrent error detection in systolic arrays. J. VLSI Signal Process. 10(3): 237-260 (1995) - [j8]Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri, Dhamin Al-Khalili:
Design techniques for fault-tolerant systolic arrays. J. VLSI Signal Process. 11(1-2): 151-168 (1995) - 1992
- [c8]F. Rouatbi, Baher Haroun, Asim J. Al-Khalili:
Power estimation tool for sub-micron CMOS VLSI circuits. ICCAD 1992: 204-209 - [c7]Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri:
Design Methodology for Fault-Tolerant Systolic Array Architectures. ICPP (2) 1992: 267-274 - 1991
- [j7]R. V. Dantu, Nikitas J. Dimopoulos, Rajni V. Patel, A. J. Al-Khalili:
Depth perception using blurring and its application in VLSI wafer probing. Mach. Vis. Appl. 5(1): 35-45 (1991) - [c6]Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri:
Area Efficient Computing Structures for Concurrent Error Detection in Systolic Architectures. ICPP (1) 1991: 484-491 - [c5]Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri:
On the Design of Optimal Fault-Tolerant Systolic Array Architecures. IPPS 1991: 352-357 - 1990
- [j6]Asim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili:
A module generator for optimized CMOS buffers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(10): 1028-1046 (1990) - [c4]Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri:
Design of optimal systolic arrays: a systematic approach. SPDP 1990: 166-173
1980 – 1989
- 1989
- [c3]Asim J. Al-Khalili, Yong Zhu, Dhamin Al-Khalili:
A Module Generator for Optimized CMOS Buffers. DAC 1989: 245-250 - 1988
- [j5]Asim J. Al-Khalili, Dhamin Al-Khalili, K. Ammar:
An algorithm for polygon conversion to boxes for VLSI layouts. Integr. 6(3): 291-308 (1988) - [c2]Ram Dantu, Nikitas J. Dimopoulos, Rajni V. Patel, Asim J. Al-Khalili:
A micro-manipulator vision in IC Manufacturing. ICRA 1988: 1455-1460 - 1985
- [j4]Asim J. Al-Khalili:
Urban traffic control - A general approach. IEEE Trans. Syst. Man Cybern. 15(2): 260-271 (1985) - [j3]Asim J. Al-Khalili:
A general approach to relative offset settings of traffic signals. IEEE Trans. Syst. Man Cybern. 15(4): 587-594 (1985) - [j2]Asim J. Al-Khalili:
The optimum green split of a cycle time. IEEE Trans. Syst. Man Cybern. 15(5): 675-681 (1985) - 1984
- [j1]Asim J. Al-Khalili:
An Algorithm for an Intelligent Arabic Computer Terminal. Int. J. Man Mach. Stud. 20(4): 331-341 (1984)
1970 – 1979
- 1973
- [c1]C. J. Macleod, Asim J. Al-Khalili:
An On-Line Optimization Procedure for an Urban Traffic System. Optimization Techniques 1973: 31-41
Coauthor Index
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