"An Accurate Logic Threshold Voltages Determination Model for CMOS Gates to ..."

Jing-Jou Tang (1999)

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DOI: 10.1109/ATS.1999.810733

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Jing-Jou Tang:
An Accurate Logic Threshold Voltages Determination Model for CMOS Gates to Facilitate Test Generation and Fault Simulation. Asian Test Symposium 1999: 81-

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