"Power-Performance Implications of Thread-level Parallelism on Chip ..."

Jian Li, José F. Martínez (2005)

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DOI: 10.1109/ISPASS.2005.1430567

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Jian Li, José F. Martínez:
Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors. ISPASS 2005: 124-134

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