"Improving DPA Resistance of Quasi Delay Insensitive Circuits Using ..."

G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard (2005)

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DOI: 10.1007/978-0-387-73661-7_2

access: open

type: Conference or Workshop Paper

metadata version: 2018-06-26

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  - conf/vlsi/BouesseRS05
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  - https://dblp.org/rec/conf/vlsi/BouesseRS05
G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard:
Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals. VLSI-SoC 2005: 11-24

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