"Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier ..."

Arish S, R. K. Sharma (2017)

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DOI: 10.1007/S00034-016-0335-2

access: closed

type: Journal Article

metadata version: 2020-06-21

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Arish S, R. K. Sharma:
Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA. Circuits Syst. Signal Process. 36(3): 998-1026 (2017)

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