"Parallel pipelined array architectures for real-time histogram computation ..."

José O. Cadenas et al. (2011)

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DOI: 10.1109/TCE.2011.6131111

access: closed

type: Journal Article

metadata version: 2020-07-09

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José O. Cadenas, Robert Simon Sherratt, Pablo Huerta, Wen-Chung Kao:
Parallel pipelined array architectures for real-time histogram computation in consumer devices. IEEE Trans. Consumer Electron. 57(4): 1460-1464 (2011)

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