default search action

combined dblp search
author search
venue search
publication search

ask others

2nd IFMT 2010: Saint-Malo, France

> Home > Conferences and Workshops > IFMT

Refine list

refinements active!

zoomed in on ?? of ?? records

view refined list in

export refined list as

showing all ?? records

- view
  authority control:
- export record
  dblp key:
  - conf/ifmt/2010
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ifmt/2010
Hisham El-Shishiny, Erven Rohou:
Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies, IFMT '10, Saint-Malo, France, June 19, 2010. ACM 2010, ISBN 978-1-4503-0008-7

Memory hierarchies for multicore processors

- view
  authority control:
- export record
  dblp key:
  - conf/ifmt/KedzierskiCGBV10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ifmt/KedzierskiCGBV10
Kamil Kedzierski, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Mateo Valero:
Power and performance aware reconfigurable cache for CMPs. 1:1-1:12
- view
  authority control:
- export record
  dblp key:
  - conf/ifmt/VegaRCRV10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ifmt/VegaRCRV10
Augusto Vega, Alejandro Rico, Felipe Cabarcas, Alex Ramírez, Mateo Valero:
Comparing last-level cache designs for CMP architectures. 2:1-2:11
- view
  authority control:
- export record
  dblp key:
  - conf/ifmt/Gu0LS10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ifmt/Gu0LS10
Junli Gu, Rakesh Kumar, Steven S. Lumetta, Yihe Sun:
Accelerating data movement on future chip multi-processors. 3:1-3:12
- view
  authority control:
- export record
  dblp key:
  - conf/ifmt/KayiE10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ifmt/KayiE10
Abdullah Kayi, Tarek A. El-Ghazawi:
An adaptive cache coherence protocol for chip multiprocessors. 4:1-4:10

Multicore architectures

- view
  authority control:
- export record
  dblp key:
  - conf/ifmt/NegiWS10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ifmt/NegiWS10
Anurag Negi, M. M. Waliullah, Per Stenström:
LV*: a class of lazy versioning HTMs for low-cost integration of transactional memory systems. 5:1-5:10
- view
  authority control:
- export record
  dblp key:
  - conf/ifmt/VentrouxD10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ifmt/VentrouxD10
Nicolas Ventroux, Raphaël David:
SCMP architecture: an asymmetric multiprocessor system-on-chip for dynamic applications. 6:1-6:12

Parallel programming

- view
  authority control:
- export record
  dblp key:
  - conf/ifmt/0002E10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ifmt/0002E10
Ahmed El-Mahdy, Hisham El-Shishiny:
Efficient parallel selective separable-kernel convolution on heterogeneous processors. 7:1-7:6
- view
  authority control:
- export record
  dblp key:
  - conf/ifmt/LorentzMA10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ifmt/LorentzMA10
István Lorentz, Mihaela Malita, Razvan Andonie:
Fitting FFT onto an energy efficient massively parallel architecture. 8:1-8:11

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.