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ORCID17th ISCA 1990: Seattle, WA, USA
- Jean-Loup Baer, Larry Snyder, James R. Goodman:
Proceedings of the 17th Annual International Symposium on Computer Architecture, Seattle, WA, USA, June 1990. ACM 1990, ISBN 0-89791-366-3 - Sarita V. Adve, Mark D. Hill:
Weak Ordering - A New Definition. 2-14 - Kourosh Gharachorloo, Daniel Lenoski, James Laudon, Phillip B. Gibbons, Anoop Gupta, John L. Hennessy:
Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors. 15-26 - Joonwon Lee, Umakishore Ramachandran:
Synchronization with Multiprocessor Caches. 27-37 - Po-Jen Chuang, Nian-Feng Tzeng:
Dynamic Processor Allocation in Hypercube Computers. 40-49 - Abdou Youssef, Bruce W. Arden:
A New Approach to Fast Control of r2 x r2 3-Stage Benes Networks of r x r Crossbar Switches. 50-59 - William J. Dally:
Virtual-Channel Flow Control. 60-68 - Shekhar Borkar, Robert Cohn, George W. Cox, Thomas R. Gross, H. T. Kung, Monica Lam, Margie Levine, Brian Moore, Wire Moore, Craig Peterson, Jim Susman, Jim Sutton, John Urbanski, Jon A. Webb:
Supporting Systolic and Memory Communciation in iWarp. 70-81 - Gregory M. Papadopoulos, David E. Culler:
Monsoon: An Explicit Token-Store Architecture. 82-91 - Marco Annaratone, Marco Fillo, Kiyoshi Nakabayashi, Marc A. Viredaz:
The K2 Parallel Processor: Architecture and Hardware Implementation. 92-101 - Anant Agarwal, Beng-Hong Lim, David A. Kranz, John Kubiatowicz:
APRIL: A Processor Architecture for Multiprocessing. 104-114 - Roberto Bisiani, Mosur Ravishankar:
PLUS: A Distributed Shared-Memory System. 115-124 - John K. Bennett, John B. Carter, Willy Zwaenepoel:
Adaptive Software Cache Management for Distributed Shared Memory Architectures. 125-134 - Brian W. O'Krafka, A. Richard Newton:
An Empirical Evaluation of Two Memory-Efficient Directory Methods. 138-147 - Daniel Lenoski, James Laudon, Kourosh Gharachorloo, Anoop Gupta, John L. Hennessy:
The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor. 148-159 - Steven A. Przybylski:
The Performance Impact of Block Sizes and Fetch Strategies. 160-169 - D. Alpert, Amir Averbuch, O. Danieli:
Performance Comparison of Load/Store and Symmetric Instruction Set Architectures. 172-181 - Jack W. Davidson, David B. Whalley:
Reducing the Cost of Branches by Using Registers. 182-191 - Carl E. Love, Harry F. Jordan:
An Investigation of Static Versus Dynamic Scheduling. 192-201 - Dileep Bhandarkar, Richard Brunner:
VAX Vector Architecture. 204-215 - Robert W. Horst, Richard L. Harris, Robert L. Jardine:
Multiple Instruction Issue in the NonStop Cyclone Processor. 216-226 - Shreekant S. Thakkar, Mark Sweiger:
Performance of an OLTP Application on Symmetry Multiprocessor System. 228-238 - Ding-Kai Chen, Hong-Men Su, Pen-Chung Yew
:
The Impact of Synchronization and Granularity on Parallel Systems. 239-248 - Hakon O. Bugge, Ernst H. Kristiansen, Bjorn O. Bakka:
Trace-Driven Simulations for a Two-Level Cache Design in Open Bus Systems. 250-259 - Jiun-Ming Hsu, Prithviraj Banerjee:
Performance Measurement and Trace Driven Simulation of Parallel CAD and Numeric Applications on a Hypercube Multicomputer. 260-269 - Anita Borg, Richard E. Kessler, David W. Wall:
Generation and Analysis of Very Long Address Traces. 270-279 - Bruce K. Holmer, Barton Sano, Michael J. Carlton, Peter Van Roy, Ralph Clarke Haygood, William R. Bush, Alvin M. Despain, Joan M. Pendleton, Tep P. Dobry:
Fast Prolog with an Extended General Purpose Architecture. 282-291 - Leon Alkalaj, Tomás Lang, Milos D. Ercegovac:
Architectural Support for the Management of Tightly-Coupled Fine-Grain Goals in Flat Concurrent Prolog. 292-301 - Samuel Ho, Lawrence Snyder:
Balance in Architectural Design. 302-310 - A. L. Narasimha Reddy, Prithviraj Banerjee:
A Study of I/O Behavior of Perfect Benchmarks on a Multiprocessor. 312-321 - Peter M. Chen, David A. Patterson:
Maximizing Performance in a Striped Disk Array. 322-331 - Kang G. Shin, Greg Dykema:
A Distributed I/O Architecture for HARTS. 332-342 - Michael D. Smith, Monica S. Lam, Mark Horowitz:
Boosting Beyond Static Scheduling in a Superscalar Processor. 344-354 - George Taylor, Peter Davies, Michael Farmwald:
The TLB Slice - A Low-Cost High-Speed Address Translation Mechanism. 355-363 - Norman P. Jouppi:
Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers. 364-373
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