default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDSoC 2009: Tampere, Finland
- 2008 IEEE International Symposium on System-on-Chip, SOC 2009, Tampere, Finland, October 6-7, 2008. IEEE 2009, ISBN 978-1-4244-4465-6
- Sohaib Majzoub
, Resve A. Saleh, Steven J. E. Wilton, Rabab Ward:
Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms. 1-4 - Heikki Kariniemi, Jari Nurmi:
Fault-tolerant communication over Micronmesh NOC with Micron Message-Passing protocol. 5-12 - Matthias Eireiner, Doris Schmitt-Landsiedel, Paul Wallner, Andreas Schöne, Stephan Henzler, Ulrich Fiedler:
Adaptive circuit block model for power supply noise analysis of low power system-on-chip. 13-18 - Heikki Orsila, Erno Salminen, Timo D. Hämäläinen:
Parameterizing simulated annealing for distributing Kahn Process Networks on multiprocessor SoCs. 19-26 - Kshitij Bhardwaj, Rabindra Ku Jena:
Energy and bandwidth aware mapping of IPs onto regular NoC architectures using Multi-Objective Genetic Algorithms. 27-31 - Volker Gierenz, Christian Panis, Jari Nurmi:
Physical realization oriented area-power-delay tradeoff exploration. 32-37 - Behnam Ghavami, Hamid R. Zarandi, Arezoo Salarpour, Hossein Pedram:
Diagnosis of faults in template-based asynchronous circuits. 38-41 - Aleksandar Milutinovic, Kees Goossens, Gerard J. M. Smit:
Dynamic workload peak detection for slack management. 42-47 - Wei Song, Doug A. Edwards:
Building asynchronous routers with independent sub-channels. 48-51 - Eric P. Kim, Rami A. Abdallah, Naresh R. Shanbhag:
Soft NMR: Exploiting statistics for energy-efficiency. 52-55 - David Szczesny, Anas Showk, Sebastian Hessel, Attila Bilgic, Uwe Hildebrand, Valerio Frascolla:
Performance analysis of LTE protocol processing on an ARM based mobile platform. 56-63 - Marco Lattuada, Christian Pilato, Antonino Tumeo, Fabrizio Ferrandi:
Performance modeling of parallel applications on MPSoCs. 64-67 - Faiz-ul Hassan, B. Cheng, Wim Vanderbauwhede, Fernando Rodríguez Salazar:
Impact of device variability in the communication structures for future synchronous SoC designs. 68-72 - Tor Skeie, Frank Olaf Sem-Jacobsen, Samuel Rodrigo, José Flich, Davide Bertozzi, Simone Medardoni:
Flexible DOR routing for virtualization of multicore chips. 73-76 - David Kammler, Bastian Bauwens, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Anupam Chattopadhyay:
Automatic generation of memory interfaces. 77-82 - Nazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine:
Two phase clocked adiabatic static CMOS logic. 83-86 - Ewerson Carvalho, César A. M. Marcon, Ney Calazans, Fernando Moraes:
Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs. 87-90 - Piia Saastamoinen, Jari Nurmi, Ilkka Saastamoinen, Mikko Laiho:
Minimizing area costs in GPS applications on a programmable DSP by code compression. 91-94 - Mihkel Tagel, Peeter Ellervee, Gert Jervan:
Scheduling framework for real-time dependable NoC-based systems. 95-99 - Samuel Rodrigo, Carles Hernández, José Flich, Federico Silla, José Duato, Simone Medardoni, Davide Bertozzi, Andres Mejia, Donglai Dai:
Yield-oriented evaluation methodology of network-on-chip routing implementations. 100-105 - Davide Rossi, Fabio Campi, Antonio Deledda, Claudio Mucci, Stefano Pucillo, Sean Whitty, Rolf Ernst, Stéphane Chevobbe, Stéphane Guyetant, Matthias Kühnle, Michael Hübner, Jürgen Becker, Wolfram Putzke-Röming:
A multi-core signal processor for heterogeneous reconfigurable computing. 106-109 - Fabio Campi, Ralf König, Michael Dreschmann, M. Neukirchner, Damien Picard, M. Jüttner, Eberhard Schüler, Antonio Deledda, Davide Rossi, Alberto Pasini, Michael Hübner, Jürgen Becker, Roberto Guerrieri:
RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip. 110-113 - Haitham Habli, Johan Lilius, Johan Ersfolk:
Analysis of memory access optimization for motion compensation frames in MPEG-4. 114-117 - Dragomir Milojevic, Riko Radojcic, Roger Carpenter, Pol Marchal:
Pathfinding: A design methodology for fast exploration and optimisation of 3D-stacked integrated circuits. 118-123 - Joël Porquet, Christian Schwarz, Alain Greiner:
Multi-compartment: A new architecture for secure co-hosting on SoC. 124-127 - Jari Nikara, Eero Aho, Petri A. Tuominen, Kimmo Kuusilinna:
Performance analysis of multi-channel memories in mobile devices. 128-131 - Di Wu, Johan Eilert, Dake Liu, Anders Nilsson, Eric Tell, Eric Alfredsson:
System architecture for 3GPP LTE modem using a programmable baseband processor. 132-137 - Zhenyu Tu, Meng Yu, Daniel Iancu, Mayan Moudgill, John Glossner:
On the performance of 3GPP LTE baseband using SB3500. 138-142 - Guillermo Payá Vayá, Javier Martín-Langerwerf, Florian Giesemann, Holger Blume, Peter Pirsch:
Instruction merging to increase parallelism in VLIW architectures. 143-146 - Arnaldo Azevedo, Ben H. H. Juurlink:
An efficient software cache for H.264 motion compensation. 147-150 - Chris Rowen, Peter R. Nuth, Stuart Fiske:
A DSP architecture optimized for wireless baseband. 151-156 - Fabio Garzia, Roberto Airoldi, Jari Nurmi, Carmelo Giliberto, Claudio Brunelli:
Mapping of the FFT on a reconfigurable architecture targeted to SDR applications. 157-160 - Stefan Kraemer, Rainer Leupers, Dietmar Petras, Thomas Philipp:
A checkpoint/restore framework for systemc-based virtual platforms. 161-167 - Paul Edward McKechnie, Michaela Blott, Wim Vanderbauwhede:
Automated instrumentation of FPGA-based systems for system-level transaction monitoring. 168-171 - Sanna Määttä, Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Manfred Glesner, Fernando Gehm Moraes, Jari Nurmi:
Characterising embedded applications using a UML profile. 172-175
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-08 20:17 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
