default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID12th LASCAS 2021: Arequipa, Peru
- 12th IEEE Latin America Symposium on Circuits and System, LASCAS 2021, Arequipa, Peru, February 21-24, 2021. IEEE 2021, ISBN 978-1-7281-7670-3
- Özgür Deniz Temel, Onur Ferhanoglu, Mustafa Berke Yelten:
Design of a Constant Current Laser Driver for Biomedical Applications. 1-4 - Alexandre B. Z. de França, Fernanda D. V. R. Oliveira, José Gabriel Rodríguez Carneiro Gomes, Nadia Nedjah:
Non-Memoryless vs. Memoryless Hardware Architectures for Convolutional Neural Networks. 1-4 - Anselm Breitenreiter
, Oliver Schrape, Marko S. Andjelkovic, Milos Krstic:
Reliability Analysis in Less than 200 Lines of Code. 1-4 - Elisabetta Moisello, Michele Vaiana, Maria Eloisa Castagna, Giuseppe Bruno, Igor Brouk, Tanya Blank, Sharon Bar-Lev, Yael Nemirovsky, Piero Malcovati, Edoardo Bonizzoni:
Study of a Voltage-Mode Readout Configuration for Micromachined CMOS Transistors for Uncooled IR Sensing. 1-4 - Marco Orna, Dominique Morche, Andrea Baschirotto, Emmanuel Allier, Patrick Arno:
Quantitative Jitter Simulations and FIR-DAC sizing for Single-Bit Continuous Time Sigma Delta Modulators. 1-4 - Laura Hernández-Alpizar, Arys Carrasquilla-Batista, Lilliana Sancho-Chavarría:
Monitoring adjustment based on current data of an IoT-COTS monitor for environmental chemical analysis. 1-4 - Arijit Karmakar, Valentijn De Smedt, Paul Leroux:
Pseudo-Differential Time-Domain Integrator Using Charge-Based Time-Domain Circuits. 1-4 - David Cordova, Wim Cops, Yann Deval, Francois Rivet, Hervé Lapuyade, Nicolas Nodenot, Yohan Piccin:
Optimized body-biasing calibration methodology for high-speed comparators in 22nm FDX. 1-4 - Luis Henrique Rodovalho, Rafael Sanchotene Silva, Cesar Ramos Rodrigues:
A 1V, 450pS OTA Based on Current-Splitting and Modified Series-Parallel Mirrors. 1-4 - Agustin C. Galetto, Benjamín T. Reyes, Damián A. Morero, Mario R. Hueda:
Background Compensation of Frequency Interleaved DAC for Optical Transceivers. 1-4 - Geaninne Lopes, Iaçanã I. Weber, César A. M. Marcon, Fernando Gehm Moraes:
Chronos: An Abstract NoC-based Manycore with Preserved Temporal and Spatial Traffic Distribution. 1-4 - Daniel Beauchamp, Keith M. Chugg:
Linearization for High-Speed Current-Steering DACs Using Neural Networks. 1-4 - Sandra George, Padmanava Sen, André Noll Barreto, Gerhard P. Fettweis:
Reconfigurable E-band Receiver Development for Joint Communication and Sensing. 1-4 - Leonardo Heitich Brendler, Alexandra L. Zimpeck, Fernanda Lima Kastensmidt, Cristina Meinhardt, Ricardo A. L. Reis:
Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit. 1-4 - Pedro Tauã Lopes Pereira, Guilherme Paim, Guilherme da Costa Ferreira, Eduardo A. C. da Costa, Sérgio Almeida, Sergio Bampi:
Exploring Approximate Adders for Power-Efficient Harmonics Elimination Hardware Architectures. 1-4 - Lionel Trojman, David Rivadeneira, Marco Villegas, Eliana Acurio, Marco Lanuzza, Luis-Miguel Procel, Ramiro Taco:
RF-DC Multiplier for RF Energy Harvester based on 32nm and TFET technologies. 1-4 - Guillermo Royo, Antonio D. Martínez-Pérez, Carlos Sánchez-Azqueta, Concepción Aldea, Santiago Celma:
Noise Reduction Technique using Multiple Photodiodes in Optical Receivers for POF Communications. 1-4 - Isadora Oliveira, Marcelo Danigno, Paulo F. Butzen, Ricardo Reis:
Benchmarking Open Access VLSI Partitioning Tools. 1-4 - Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis:
Current Behavior on Process Variability Aware FinFET Inverter Designs. 1-4 - Oliver Schrape, Anselm Breitenreiter, Carsten Schulze, Steffen Zeidler, Milos Krstic:
Radiation-Hardness-by-Design Latch-based Triple Modular Redundancy Flip-Flops. 1-4 - Miguel Garcia-Bosque, Guillermo Díez-Señorans, Carlos Sánchez-Azqueta, Santiago Celma:
FPGA Implementation of a New PUF Based on Galois Ring Oscillators. 1-4 - Luiz Neto, Marcel Moscarelli Corrêa, Daniel Palomino, Luciano Agostini, Guilherme Corrêa:
Exploring Operation Sharing in Directional Intra Frame Prediction of AV1 Video Coding. 1-4 - Augusto W. Hoppe, Jürgen Becker, Fernanda Lima Kastensmidt:
High-speed Hardware Accelerator for Trace Decoding in Real-Time Program Monitoring. 1-4 - Gordana Jovanovic-Dolecek, José M. de la Rosa:
Low-Power Compensated Modified Comb Decimation Structure for Power-of-Two Decimation Factors. 1-4 - Nisha Gupta, Ashudeb Dutta, Shiv Govind Singh:
A Novel Down Conversion Mixer with Low/High Band Re-configurable Transconductance Amplifier in 65nm CMOS Process. 1-4 - Shelby Critcher, Todd J. Freeborn:
Residual Impedance Impact on MAX30001 Accuracy for Bioimpedance Applications. 1-4 - Maide Bucolo, Arturo Buscarino, Luigi Fortuna, Mattia Frasca:
Towards analog computing devices for matrix algebraic problems. 1-4 - Daniel Patricio Nicolalde Rodríguez, José Antonio Apolinário, Wallace A. Martins:
Robust Passive Coherent Location via Nonlinearly Constrained Least Squares. 1-4 - Kostas Touloupas, Paul-Peter Sotiriadis:
Analog and RF Circuit Constrained Optimization Using Multi-Objective Evolutionary Algorithms. 1-4 - Carolina Teng, Renan W. Achjian, Caio C. Braga, Marcelo Knörich Zuffo, Wang Jiang Chau:
Accelerating the base-level alignment step of DNA assembling in Minimap2 Algorithm using FPGA. 1-4 - Ricardo Escobar, Luis-Miguel Prócel, Lionel Trojman, Marco Lanuzza, Ramiro Taco:
High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. 1-4 - Jeferson González-Gómez, Steven Ávila-Ardón, Jonathan Rojas-González, Andres Stephen-Cantillano, Jorge Castro-Godínez, Carlos Salazar-García, Muhammad Shafique, Jörg Henkel:
TailoredCore: Generating Application-Specific RISC-V-based Cores. 1-4 - Duarte Lopes de Oliveira, Gabriel C. Duarte, Gracieth Cavalcanti Batista:
A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication. 1-4 - Abderrahmane Ghimouz, Fatah Rarbi, Olivier Rossetto:
Systematic high-level design of a fifth order Continuous-Time CRFF Delta Sigma ADC. 1-4 - Kevin Sosa, Horacio Failache, Julián Oreggioni:
Design and implementation of a trans-impedance amplifier for a miniaturized saturated absorption spectrometer. 1-4 - Andrea Floridia, Ernesto Sánchez:
A JTAG-based Fault Emulation Platform for Dependability Analyses of Processor-based ASICs. 1-4 - Markus Fritscher, Johannes Knödtel, Daniel Reiser, Maen Mallah, Stefan Pechmann, Dietmar Fey, Marc Reichenbach:
Simulating large neural networks embedding MLC RRAM as weight storage considering device variations. 1-4 - Ana C. A. Barbosa, Juan C. Castellanos:
On-chip Diffusion Charge Redistribution Ladder Converter for Photovoltaic Systems with Mismatch. 1-4 - Álvaro Fernandez Bocco, Fredy Solis, Benjamín T. Reyes, Damián A. Morero, Mario R. Hueda:
An Error Backpropagation-based Background Calibration of Pipeline TI-ADCs for 256-QAM Optical Coherent Receivers. 1-4 - Mustafa Sedat Berk, Benan Beril Inam, Mustafa Berke Yelten:
An ISM-Band Multi-Phase Injection-Locked Ring Oscillator. 1-4 - Thomas Eleftherios Dimitrios Kizas, Lorenzo Crespi, Piero Malcovati, Andrea Baschirotto:
A Library of High-Level Models for the Simulation of DC-DC Converters. 1-4 - Patrick Valet, David Schwingshackl, Andrea M. Tonello:
Comparative Study on Pre-Distortion/Calibration Methods for Current-Steering Digital-to-Analog Converters. 1-4 - Felipe Pinto, Ioannis Vourkas:
Design Considerations for the Development of Computational Resistive Memories. 1-4 - Antonio D. Martínez-Pérez, Pedro A. Martínez Martínez, Francisco Aznar, Guillermo Royo, Santiago Celma:
A Strategy to Achieve Competitive Performance in Basic RF LNAs. 1-4 - Todd J. Freeborn, Shelby Critcher:
Estimating Cole-Impedance Parameters from Limited Frequency-Band Impedance Measurements. 1-4 - Hugo Daniel Hernández, Diego Augusto Pontes, Tarciso A. Martins, David Reyes, Wilhelmus A. M. Van Noije:
ISFET Array Readout System with Integrated 12 bit A/D Conversion for Lab-on-Chip Applications. 1-4 - L. Wesley Passos, Gabriel M. Araujo, Jonathan N. Gois, Amaro A. de Lima:
A Brazilian Sign Language Gesture Recognizing System Using Gait Energy Image. 1-4 - Ash Luft, Mihai Sima, Michael McGuire:
Hardware Trojan with Frequency Modulation. 1-4 - Shahriar Shahabuddin, Mahmoud A. M. Albreem, Mohammad Shahanewaz Shahabuddin, Zaheer Khan, Markku J. Juntti:
FPGA Implementation of Stair Matrix based Massive MIMO Detection. 1-4 - Muhammed Mustafa Kizmaz, Salih Ergün:
A CMOS Implementation of the Tent Map for Random Number Generation. 1-4 - Maria Eduarda de Melo Hang, Cleiton Magano Marques, Paulo F. Butzen, Cristina Meinhardt:
Soft Error Sensibility Window at FinFET DICE SRAM. 1-4 - Carlos A. Pinheiro, Fabián Olivera, Antonio Petraglia:
A Three-Stage Charge Pump with Forward Body Biasing in 28 nm UTBB FD-SOI CMOS. 1-4 - Sheetal Barekar, Madan Mali:
On-Chip Area and Test Time Effective Weak Resistive Open Defect Detection Technique for Cache Memory. 1-4 - Bastian Lindner, Niko Joram, Frank Ellinger:
Ultra Low Power < 9 nW Adaptive Duty Cycling Oscillator in 22 nm FDSOI CMOS Technology using Back Gate Biasing. 1-4 - Francois Rivet, Laura Foucaud, Guillaume Ferré:
Edge Computing Technique for a 87% Energy Saving for IoT Device Dedicated to Environmental Monitoring. 1-4 - David Cordova, Wim Cops, Yann Deval, Francois Rivet, Hervé Lapuyade, Nicolas Nodenot, Yohan Piccin:
Design methodology for 112Gb/s PAM4 Wireline ADC-Based Receivers. 1-4 - M. Agius, Clive Seguna, Judie Attard, Kris Scicluna, Jeremy Scerri:
A Wearable Wireless Sensing System for Capturing Human Arm Motion. 1-4 - Mariana C. Toledo, Sandro M. Marques, Thiarles S. Medeiros, Fábio Diniz Rossi, Marcelo Caggiani Luizelli, Antonio Carlos Schneider Beck, Arthur Francisco Lorenzon:
EDP Optimization of Parallel Applications via CPU Frequency Scaling on AMD Processors. 1-4 - David Ponce, Alexandre de Jesus Aragão, Bruno Sanches, Wilhelmus A. M. Van Noije:
Assessment of key parameters in a microwave imaging system design for breast cancer detection. 1-4 - Leonardo Rezende Juracy, Matheus T. Moreira, Alexandre M. Amory, Fernando Gehm Moraes:
A TensorFlow and System Simulator Integration Approach to Estimate Hardware Metrics of Convolution Accelerators. 1-4 - Alexandre Quenon, Evelyne Daubie, Véronique Moeyaert, Fortunato Carlos Dualibe:
On the Possibility to Use Energy Harvesting on Beta Radiation in Nuclear Environments. 1-4 - Fernando L. Aguirre, Sebastián Matías Pazos, Felix Palumbo, N. Gomez, Enrique Miranda, Jordi Suñé:
Line Resistance Impact in Memristor-based Multi Layer Perceptron for Pattern Recognition. 1-4 - Gracieth Cavalcanti Batista, Duarte Lopes de Oliveira, Osamu Saotome:
New Low-Power Architectures of Support Vector Machine Classifier for Speech Recognition System. 1-4 - Guilherme da Costa Ferreira, Pedro Tauã Lopes Pereira, Guilherme Paim, Eduardo A. C. da Costa, Sergio Bampi:
A Power-Efficient FFT Hardware Architecture Exploiting Approximate Adders. 1-4 - Geancarlo Abich, Ricardo Reis, Luciano Ost:
The Impact of Precision Bitwidth on the Soft Error Reliability of the MobileNet Network. 1-4
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-04-03 00:02 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
