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ORCID44th MICRO 2011: Porto Alegre, Brazil
- Carlo Galuzzi, Luigi Carro, Andreas Moshovos, Milos Prvulovic:
44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, Porto Alegre, Brazil, December 3-7, 2011. ACM 2011, ISBN 978-1-4503-1053-6
Best paper candidates A
- Charles Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm Allen-Ware, Bishop Brock, José A. Tierno, John B. Carter:
Active management of timing guardband to save energy in POWER7. 1-11 - Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott A. Mahlke, David I. August:
Bundled execution of recurring traces for energy-efficient general purpose processing. 12-23 - Dimitris Kaseridis, Jeffrey Stuecheli, Lizy Kurian John:
Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era. 24-35
Best paper candidates B
- Mitchell Hayenga, Mikko H. Lipasti:
The NoX router. 36-46 - Konstantinos Aisopos, Li-Shiuan Peh:
A systematic methodology to develop resilient cache coherence protocols. 47-58 - Gagan Gupta, Gurindar S. Sohi:
Dataflow execution of sequential imperative programs on multicore architectures. 59-70
NoCs
- Tushar Krishna, Li-Shiuan Peh, Bradford M. Beckmann, Steven K. Reinhardt:
Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication. 71-82 - George Michelogiannakis
, Nan Jiang, Daniel Becker, William J. Dally:
Packet chaining: efficient single-cycle allocation for on-chip networks. 83-94 - Christopher Nitta, Matthew K. Farrens, Venkatesh Akella:
Resilient microring resonator based photonic networks. 95-104 - Yan Pan, John Kim, Gokhan Memik:
FeatherWeight: low-cost optical arbitration with QoS support. 105-116
Speculation
- André Seznec:
A new case for the TAGE branch predictor. 117-127 - Jing Xin, Russ Joseph:
Identifying and predicting timing-critical instructions to boost timing speculation. 128-139 - Marc de Kruijf, Karthikeyan Sankaralingam:
Idempotent processor architecture. 140-151 - Michael Ferdman, Cansu Kaynak, Babak Falsafi:
Proactive instruction fetch. 152-162
Energy efficiency
- Ganesh Venkatesh, Jack Sampson, Nathan Goulding-Hotta, Sravanthi Kota Venkata, Michael Bedford Taylor, Steven Swanson:
QsCores: trading dark silicon for scalable energy efficiency with quasi-specific cores. 163-174 - Ryan Cochran, Can Hankendi, Ayse K. Coskun, Sherief Reda:
Pack & Cap: adaptive DVFS and thread packing under power caps. 175-185 - Andrew W. Hay, Karin Strauss, Timothy Sherwood, Gabriel H. Loh, Doug Burger:
Preventing PCM banks from seizing too much power. 186-195 - Vignyan Reddy Kothinti Naresh, David J. Palframan, Mikko H. Lipasti:
CRAM: coded registers for amplified multiporting. 196-205
Multi-core programmability
- Jiaqi Zhang, Weiwei Xiong, Yang Liu, Soyeon Park, Yuanyuan Zhou, Zhiqiang Ma:
ATDetector: improving the accuracy of a commercial data race detector by identifying address transfer. 206-215 - Gilles Pokam, Cristiano Pereira, Shiliang Hu, Ali-Reza Adl-Tabatabai, Justin Emile Gottschlich, Jungwoo Ha, Youfeng Wu:
CoreRacer: a practical memory race recorder for multicore x86 TSO processors. 216-225 - Jesse G. Beu, Michel C. Rosier, Thomas M. Conte:
Manager-client pairing: a framework for implementing coherence hierarchies. 226-236 - Ahmed H. Abdel-Gawad, Mithuna Thottethodi:
TransCom: transforming stream communication for load balance and efficiency in networks-on-chip. 237-247
Datacenters and virtualization
- Jason Mars, Lingjia Tang, Robert Hundt, Kevin Skadron, Mary Lou Soffa:
Bubble-Up: increasing utilization in modern warehouse scale computers via sensible co-locations. 248-259 - Sheng Li, Kevin T. Lim, Paolo Faraboschi, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi:
System-level integrated server architectures for scale-out datacenters. 260-271 - Seongwook Jin, Jeongseob Ahn, Sanghoon Cha, Jaehyuk Huh:
Architectural support for secure virtualization under a vulnerable hypervisor. 272-283
Exploiting parallelism
- Nikolas Ioannou, Marcelo Cintra:
Complementing user-level coarse-grain parallelism with implicit speculative parallelism. 284-295 - Wilson W. L. Fung, Inderpreet Singh, Andrew Brownsword, Tor M. Aamodt:
Hardware transactional memory for GPU architectures. 296-307 - Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt:
Improving GPU performance via large warps and two-level warp scheduling. 308-317
Memory technologies
- Moinuddin K. Qureshi:
Pay-As-You-Go: low-overhead hard-error correction for phase change memories. 318-328 - Zhenyu Sun, Xiuyuan Bi, Hai (Helen) Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, Wenqing Wu:
Multi retention level STT-RAM cache designs with a dynamic refresh scheme. 329-338 - Qing Guo, Xiaochen Guo, Yuxin Bai, Engin Ipek:
A resistive TCAM accelerator for data-intensive computing. 339-350
Memory
- Gabriel H. Loh:
A register-file approach for row buffer caches in die-stacked DRAMs. 351-361 - Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, José A. Joao, Onur Mutlu, Yale N. Patt:
Parallel application memory scheduling. 362-373 - Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut T. Kandemir, Thomas Moscibroda:
Reducing memory interference in multicore systems via application-aware memory channel partitioning. 374-385
Validation and reliability
- Nikos Foutris, Dimitris Gizopoulos, Mihalis Psarakis, Xavier Vera, Antonio González:
Accelerating microprocessor silicon validation by exposing ISA diversity. 386-397 - Shuguang Feng, Shantanu Gupta, Amin Ansari, Scott A. Mahlke, David I. August:
Encore: low-cost, fine-grained transient fault recovery. 398-409 - Ritesh Parikh, Valeria Bertacco:
Formally enhanced runtime verification to ensure NoC functional correctness. 410-419
Caches
- Soontae Kim, Jongmin Lee, Jesung Kim, Seokin Hong:
Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits. 420-429 - Carole-Jean Wu, Aamer Jaleel, William Hasenplaugh, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer:
SHiP: signature-based hit predictor for high performance caching. 430-441 - Carole-Jean Wu, Aamer Jaleel, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer:
PACMan: prefetch-aware cache management for high performance caching. 442-453 - Gabriel H. Loh, Mark D. Hill:
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches. 454-464
Compiler support
- Mark Gebhart, Stephen W. Keckler, William J. Dally:
A compile-time managed multi-level register file hierarchy. 465-476 - Gregory Frederick Diamos, Benjamin Ashbaugh, Subramaniam Maiyuran, Andrew Kerr, Haicheng Wu, Sudhakar Yalamanchili:
SIMD re-convergence at thread frontiers. 477-488 - Yuanrui Zhang, Wei Ding, Mahmut T. Kandemir, Jun Liu, Ohyoung Jang:
A data layout optimization framework for NUCA-based multicores. 489-500
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