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2020 – today
- 2024
[c49]You-En Wu, Hsin-I Wu, Kuo-Cheng Chin, Yi-Chun Yang, Ren-Song Tsay:
Accelerate Large Language Model Inference on Edge TPU with OpenVX framework. AICAS 2024: 502-506- [c48]Hsuan-Yi Lin, Ren-Song Tsay:
Beyond Time-Quantum: A Basic-Block FDA Approach for Accurate System Computing Performance Estimation. ASPDAC 2024: 698-703 - 2023
- [c47]Yi-Chun Yang, Ren-Song Tsay:
Ureka: A Decentralized and Secure System for Managing Personal IoT Devices. ICCE-Taiwan 2023: 141-142 - [c46]Wei-Hsin Chang, Ren-Song Tsay:
A Secure and Reliable Private Key Recovery Method. ICCE-Taiwan 2023: 535-536 - [c45]Yi-Chun Yang, Ren-Song Tsay:
A Decentralized Solution for Secure Management of IoT Access Rights. ICR 2023: 213-224 - 2022
- [c44]Hsu-Hsun Chin, Ren-Song Tsay, Hsin-I Wu:
An Adaptive High-Performance Quantization Approach for Resource-Constrained CNN Inference. AICAS 2022: 336-339 - [c43]Chong-Yin Lu, Ren-Song Tsay, Weyshin Chang:
An Embedded CNN Design for Edge Devices Based on Logarithmic Computing. VLSI-DAT 2022: 1-4 - [i11]Wei-Hsin Chang, Ren-Song Tsay:
An Owner-managed Indirect-Permission Social Authentication Method for Private Key Recovery. CoRR abs/2209.09388 (2022) - 2021
- [i10]Hsu-Hsun Chin, Ren-Song Tsay, Hsin-I Wu:
A High-Performance Adaptive Quantization Approach for Edge CNN Applications. CoRR abs/2107.08382 (2021) - [i9]Yun Chang, Hsin-I Wu, Ren-Song Tsay:
An Effective Parallel Program Debugging Approach Based on Timing Annotation. CoRR abs/2109.04142 (2021) - [i8]Li-Chun Chen, Hsin-I Wu, Ren-Song Tsay:
Automatic Timing-Coherent Transactor Generation for Mixed-level Simulations. CoRR abs/2109.04148 (2021) - [i7]Chien-Hao Chen, Ren-Song Tsay:
Analytical Process Scheduling Optimization for Heterogeneous Multi-core Systems. CoRR abs/2109.04605 (2021) - [i6]Cheng-Lin Tsai, Ren-Song Tsay:
A Fast-and-Effective Early-Stage Multi-level Cache Optimization Method Based on Reuse-Distance Analysis. CoRR abs/2109.04614 (2021) - [i5]Hsin-Yu Ho, Ren-Song Tsay:
An Effective Early Multi-core System Shared Cache Design Method Based on Reuse-distance Analysis. CoRR abs/2109.04621 (2021) - [i4]Hsuan-Yi Lin, Ren-Song Tsay:
A Precise Program Phase Identification Method Based on Frequency Domain Analysis. CoRR abs/2109.05896 (2021) - [i3]Zheng-Xun Jiang, Ren-Song Tsay:
A Double-Linked Blockchain Approach Based on Proof-of-Refundable-Tax Consensus Algorithm. CoRR abs/2109.06520 (2021) - [i2]Wei-Yi Kuo, Ren-Song Tsay:
3LSAA: A Secure And Privacy-preserving Zero-knowledge-based Data-sharing Approach Under An Untrusted Environment. CoRR abs/2110.06413 (2021) - 2020
- [j10]Hsin-I Wu
, Da-Yi Guo, Ren-Song Tsay:
A Virtualization-Assisted Full-System Simulation Approach for the Verification of System Intercomponent Interactions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5211-5224 (2020) - [c42]Hsin-I Wu, Da-Yi Guo, Hsu-Hsun Chin, Ren-Song Tsay:
A Pipeline-Based Scheduler for Optimizing Latency of Convolution Neural Network Inference over Heterogeneous Multicore Systems. AICAS 2020: 46-49 - [c41]Yin-Chun Ling, Hsu-Hsun Chin, Hsin-I Wu, Ren-Song Tsay:
Designing A Compact Convolutional Neural Network Processor on Embedded FPGAs. GCAIoT 2020: 1-7 - [c40]Asheen Lateilla Richards, Ren-Song Tsay:
An Optimal Slack-Based Course Scheduling Algorithm for Personalised Study Plans. ICEIT 2020: 1-7 - [c39]Kuo-Cheng Chin, Ren-Song Tsay, Hsin-I Wu:
A Heuristic Region-based Concurrency Bug Testing Approach. ISPA/BDCloud/SocialCom/SustainCom 2020: 1126-1135 - [c38]Hsin-I Wu, Ren-Song Tsay, Hsu-Hsun Chin:
VIRA: a virtualization assisted deterministic system-level simulations. SAC 2020: 596-598 - [c37]Hsin-I Wu, Ren-Song Tsay, Fong-Yuan Chang:
CORONA: A k-COnnected RObust Interconnection Network Generation Algorithm. VLSI-DAT 2020: 1-4 - [i1]Tsung-Ying Lu, Hsu-Hsun Chin, Hsin-I Wu, Ren-Song Tsay:
A Very Compact Embedded CNN Processor Design Based on Logarithmic Computing. CoRR abs/2010.11686 (2020)
2010 – 2019
- 2018
- [c36]Hsin-I Wu, Chi-Kang Chen, Tsung-Ying Lu, Ren-Song Tsay:
A highly efficient full-system virtual prototype based on virtualization-assisted approach. DATE 2018: 285-288 - 2016
- [c35]Chi-Kang Chen, Hsin-I Wu, Chi-Ting Hsiao, Ren-Song Tsay:
An accurate and flexible early memory system power evaluation approach using a microcomponent method. CODES+ISSS 2016: 3:1-3:8 - [c34]Hsuan-Man Chen, Chi-Kang Chen, Hsin-I Wu, Ren-Song Tsay:
Poster Paper: An Accurate Crowdsourcing-Based Adaptive Fall Detection Approach Using Smart Devices. ICHI 2016: 304 - [c33]Hsuan-Man Chen, Chi-Kang Chen, Hsin-I Wu, Ren-Song Tsay:
An Accurate Crowdsourcing-Based Adaptive Fall Detection Approach Using Smart Devices. ICHI 2016: 456-460 - 2015
- [j9]Jyun-Hao Chang, Hsin-I Wu, Hsien-Lun Pai, Ren-Song Tsay, Wai-Kei Mak:
Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1822-1835 (2015) - [c32]Li-Chun Chen, Hsin-I Wu, Ren-Song Tsay:
Automatic timing-coherent transactor generation for mixed-level simulations. ASP-DAC 2015: 588-593 - [c31]Zih-Ci Huang, Chi-Kang Chen, Ren-Song Tsay:
AROMA: A highly accurate microcomponent-based approach for embedded processor power analysis. ASP-DAC 2015: 761-766 - 2014
- [c30]Shu-Yung Chen, Chien-Hao Chen, Ren-Song Tsay:
An activity-sensitive contention delay model for highly efficient deterministic full-system simulations. DATE 2014: 1-6 - 2013
- [j8]Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen:
MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(10): 1557-1568 (2013) - [j7]Meng-Huan Wu, Cheng-Yang Fu, Peng-Chih Wang, Ren-Song Tsay:
A distributed timing synchronization technique for parallel multi-core instruction-set simulation. ACM Trans. Embed. Comput. Syst. 12(1s): 54:1-54:24 (2013) - [j6]Chen Kang Lo, Mao Lin Li, Li-Chun Chen, Yi-Shan Lu, Ren-Song Tsay, Hsu-Yao Huang, Jen-Chieh Yeh:
Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus. ACM Trans. Embed. Comput. Syst. 13(1s): 37:1-37:25 (2013) - [c29]Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen:
A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules. ASP-DAC 2013: 175-180 - [c28]Bo-Han Zeng, Ren-Song Tsay, Ting-Chi Wang:
An efficient hybrid synchronization technique for scalable multi-core instruction set simulations. ASP-DAC 2013: 588-593 - [c27]Fan-Wei Yu, Bo-Han Zeng, Yu-Hung Huang, Hsin-I Wu, Che-Rung Lee, Ren-Song Tsay:
A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulations. DATE 2013: 643-648 - [c26]Chien-Min Lee, Chi-Kang Chen, Ren-Song Tsay:
A basic-block power annotation approach for fast and accurate embedded software power estimation. VLSI-SoC 2013: 118-123 - [c25]Mao Lin Li, Chen Kang Lo, Li-Chun Chen, Jen-Chieh Yeh, Ren-Song Tsay:
A Cycle Count Accurate TLM bus modeling approach. VLSI-DAT 2013: 1-4 - [c24]Pei-Chia Patty Lin, Evason Du, Ren-Song Tsay:
A fast and accurate instruction-oriented processor simulation approach. VLSI-DAT 2013: 1-5 - 2012
- [j5]Meng-Huan Wu, Peng-Chih Wang, Cheng-Yang Fu, Ren-Song Tsay:
An Extended SystemC Framework for Efficient HW/SW Co-Simulation. ACM Trans. Design Autom. Electr. Syst. 17(2): 11:1-11:16 (2012) - [c23]Yu-Hung Huang, Yi-Shan Lu, Hsin-I Wu, Ren-Song Tsay:
A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation. DAC 2012: 127-132 - 2011
- [j4]Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, Ren-Song Tsay, Cyuan-Jhe Wu:
Real-Time Tone-Mapping Processor with Integrated Photographic and Gradient Compression using 0.13 μm Technology on an Arm Soc Platform. J. Signal Process. Syst. 64(1): 93-107 (2011) - [c22]Fong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak:
Cut-demand based routing resource allocation and consolidation for routability enhancement. ASP-DAC 2011: 533-538 - [c21]Meng-Huan Wu, Peng-Chih Wang, Cheng-Yang Fu, Ren-Song Tsay:
A high-parallelism distributed scheduling mechanism for multi-core instruction-set simulation. DAC 2011: 339-344 - [c20]Peng-Chih Wang, Meng-Huan Wu, Ren-Song Tsay:
DOM: A Data-dependency-Oriented Modeling approach for efficient simulation of OS preemptive scheduling. DATE 2011: 335-340 - [c19]Chen Kang Lo, Li-Chun Chen, Meng-Huan Wu, Ren-Song Tsay:
Cycle-count-accurate processor modeling for fast and accurate system-level simulation. DATE 2011: 341-346 - [c18]Cheng-Yang Fu, Meng-Huan Wu, Ren-Song Tsay:
A shared-variable-based synchronization approach to efficient cache coherence simulation for multi-core systems. DATE 2011: 347-352 - [c17]Ren-Song Tsay:
From academic ideas to practical physical design tools. ISPD 2011: 9-12 - 2010
- [c16]Kai-Li Lin, Chen Kang Lo, Ren-Song Tsay:
Source-level timing annotation for fast and accurate TLM computation model generation. ASP-DAC 2010: 235-240 - [c15]Meng-Huan Wu, Wen-Chuan Lee, Chen-Yu Chuang, Ren-Song Tsay:
Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation. DATE 2010: 1177-1182
2000 – 2009
- 2009
- [c14]Chen Kang Lo, Ren-Song Tsay:
Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model. ASP-DAC 2009: 558-563 - [c13]Yi-Len Lo, Mao Lin Li, Ren-Song Tsay:
Cycle count accurate memory modeling in system level design. CODES+ISSS 2009: 287-294 - [c12]Meng-Huan Wu, Cheng-Yang Fu, Peng-Chih Wang, Ren-Song Tsay:
An effective synchronization approach for fast and accurate multi-core instruction-set simulation. EMSOFT 2009: 197-204 - [c11]Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak:
How to consider shorts and guarantee yield rate improvement for redundant wire insertion. ICCAD 2009: 33-38 - 2008
- [c10]Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Rong Chen, Rong Yang, Ren-Song Tsay:
Design optimization of a global/local tone mapping processor on arm SOC platform for real-time high dynamic range video. ICIP 2008: 1400-1403 - [c9]Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, Ren-Song Tsay:
A 100MHz real-time tone mapping processor with integrated photographic and gradient compression in 0.13 mum technology. SiPS 2008: 25-30 - 2007
- [c8]Ren-Song Tsay:
An Entrepreneurship Emulation Platform. MSE 2007: 63-64
1990 – 1999
- 1993
- [j3]Ren-Song Tsay:
An exact zero-skew clock routing algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(2): 242-249 (1993) - 1992
- [c7]Minshine Shih, Ernest S. Kuh, Ren-Song Tsay:
Performance-Driven System Partitioning on Multi-Chip Modules. DAC 1992: 53-56 - [c6]Jan-Ming Ho, Ren-Song Tsay:
Clock tree regeneration. Great Lakes Symposium on VLSI 1992: 198-203 - 1991
- [j2]Gopalakrishnan Vijayan, Ren-Song Tsay:
A new method for floor planning using topological constraint reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(12): 1494-1501 (1991) - [c5]Ren-Song Tsay, Jürgen Koehl:
An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement. DAC 1991: 620-625 - [c4]Ren-Song Tsay:
Exact Zero Skew. ICCAD 1991: 336-339 - 1990
- [c3]Gopalakrishnan Vijayan, Ren-Song Tsay:
Floorplanning by Topological Constraint Reduction. ICCAD 1990: 106-109
1980 – 1989
- 1989
- [c2]Tai-Ming Parng, Ren-Song Tsay:
A new approach to sea-of-gates global routing. ICCAD 1989: 52-55 - 1988
- [j1]Ren-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu:
PROUD: a sea-of-gates placement algorithm. IEEE Des. Test 5(6): 44-56 (1988) - [c1]Ren-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu:
Proud: A Fast Sea-of-Gates Placement Algorithm. DAC 1988: 318-323
Coauthor Index
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