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ORCIDJong-Sam Kim
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2020 – today
- 2020
[j3]Dongkyun Kim, Kibong Koo, Yongmi Kim, Dong-Uk Lee, Jaejin Lee, Ki Hun Kwon, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Jong-Sam Kim, Seungwook Oh, Minsu Park, Dain Im, Yongsung Lee, Mingyu Park, Jonghyuck Choi, Junhyun Chun, Kyowon Jin, Sungchun Jang, Jun-Yong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Changhyun Kim, Minsik Han:
A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx. IEEE J. Solid State Circuits 55(1): 167-177 (2020)
2010 – 2019
- 2019
- [c3]Dongkyun Kim, Minsu Park, Sungchun Jang, Jun-Yong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Jaeil Kim, Changhyun Kim, Kyung Whan Kim, Kibong Koo, Seonghwi Song, Yongmi Kim, Dong-Uk Lee, Jaejin Lee, Dae Suk Kim, Ki Hun Kwon, Minsik Han, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Yeonuk Kim, Jong-Sam Kim, Sanghui Kim, Youngsuk Seo, Seungwook Oh, Dain Im, Haksong Kim, Jonghyuck Choi, Jinil Chung, Changhyun Lee, Yongsung Lee, Joo-Hwan Cho, Junhyun Chun, Jonghoon Oh:
A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme. ISSCC 2019: 380-382 - 2014
- [c2]Hyun-Woo Lee, Junyoung Song, Sangah Hyun, Seunggeun Baek, Yuri Lim, Jungwan Lee, Minsu Park, Haerang Choi, Changkyu Choi, Jin-Youp Cha, Jaeil Kim, Hoon Choi, Seung-Wook Kwack, Yonggu Kang, Jongsam Kim, Junghoon Park, Jonghwan Kim, Jin-Hee Cho, Chulwoo Kim, Yunsaing Kim, Jaejin Lee, Byong-Tae Chung, Sung-Joo Hong:
25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. ISSCC 2014: 434-435 - 2013
- [c1]Soo-Min Lee, Jong-Hoon Kim, Jong-Sam Kim, Yunsaing Kim, Hyunbae Lee, Jae-Yoon Sim, Hong-June Park:
A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX. ISSCC 2013: 308-309 - 2012
- [j2]Hyun-Woo Lee, Hoon Choi, Beom-Ju Shin, Kyung-Hoon Kim, Kyung Whan Kim, Jaeil Kim, Kwang Hyun Kim, Jongho Jung, Jae-Hwan Kim, Eun Young Park, Jong-Sam Kim, Jong-Hwan Kim, Jin-Hee Cho, Nam Gyu Rye, Jun Hyun Chun, Yunsaing Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung:
A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces. IEEE J. Solid State Circuits 47(6): 1436-1447 (2012)
2000 – 2009
- 2009
- [j1]Hae-Kang Jung, Kyoungho Lee, Jong-Sam Kim, Jae-Jin Lee, Jae-Yoon Sim, Hong-June Park:
A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control. IEEE J. Solid State Circuits 44(11): 2891-2900 (2009)
Coauthor Index
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