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ORCIDFumiyuki Yamane
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2000 – 2009
- 2008
[c2]Fumihiko Tachibana, Hironori Sato, Takahiro Yamashita, Hiroyuki Hara, Takeshi Kitahara, Shuou Nomura, Fumiyuki Yamane, Yoshiro Tsuboi, Keiko Seki, Shuuji Matsumoto, Yoshinori Watanabe, Mototsugu Hamada:
A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design. CICC 2008: 29-32- [c1]Shuou Nomura, Fumihiko Tachibana, Tetsuya Fujita, Chen Kong Teh, Hiroyuki Usui, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Hiroyuki Hara, Takahiro Yamashita, Jun Tanabe, Masaru Uchiyama, Yoshiro Tsuboi, Takashi Miyamori, Takeshi Kitahara, Hironori Sato, Y. Homma, Shuuji Matsumoto, Keiko Seki, Y. Watanabe, Mototsugu Hamada, Makoto Takahashi:
A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology. ISSCC 2008: 262-263
1990 – 1999
- 1998
- [j1]Tadahiro Kuroda, Kojiro Suzuki, Shinji Mita, Tetsuya Fujita, Fumiyuki Yamane, Fumihiko Sano, Akihiko Chiba, Yoshinori Watanabe, Koji Matsuda, Takeo Maeda, Takayasu Sakurai, Tohru Furuyama:
Variable supply-voltage scheme for low-power high-speed CMOS digital design. IEEE J. Solid State Circuits 33(3): 454-462 (1998)
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