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2020 – today
- 2023
[c33]Hongmin He
, Danfeng Qiu, Fen Ge:
FPGA implementation and verification of efficient and reconfigurable CNN-LSTM accelerator design. AIBDF 2023: 245-250- [c32]Wenqiang Gong, Fang Zhou, Fen Ge:
A Multi-mode Convolution Coprocessor Based on RISC-V Instruction Set Architecture. ASICON 2023: 1-5 - [c31]Jiantao Ye, Fen Ge, Fang Zhou:
A Method of Mapping Convolutional Neural Networks on Resource-limited NoC Platform. ASICON 2023: 1-4 - [c30]Guohui Zhang, Fen Ge, Fang Zhou:
A Deep Q Network Hardware Accelerator Based on Heterogeneous Computing. ASICON 2023: 1-4 - [c29]Jin Zhao, Fang Zhou, Fen Ge, Shuning Wu, Hao Wang:
A Lightweight BiSeNet Embedded with YOLOv5 Feature Fusion Network. ICCT 2023: 608-612 - 2022
- [c28]Kaiyu Zhao, Fang Zhou, Ning Wu, Jin Zhao, Fen Ge:
The Design of a Novel Hardware Trojan without Inactive Signal for AES. ICCT 2022: 1159-1163 - [c27]Zhixiang Xu, Ning Wu, Fang Zhou, Fen Ge:
A Defense Method Against Persistent Fault Attack. ICCT 2022: 1323-1327 - [c26]Hao Wang, Danfeng Qiu, Fen Ge, Ying Yang:
Implementation of Bidirectional LSTM Accelerator Based on FPGA. ICCT 2022: 1512-1516 - [c25]Ziyu Li, Fen Ge, Fang Zhou, Ning Wu:
An A3C Deep Reinforcement Learning FPGA Accelerator based on Heterogeneous Compute Units. ICCT 2022: 1521-1525 - [c24]Xinyu Wang, Ning Wu, Fang Zhou, Fen Ge:
Efficient Configurable Digit-Serial Multiplier Based on Improved Karatsuba Algorithm over GF(2m). ICCT 2022: 1531-1535 - [c23]Xin Yue, Fen Ge, Fang Zhou, Ning Wu, Yi Zhang:
A Hybrid CNN Compression Approach for Hardware Acceleration. ICCT 2022: 1546-1550 - [c22]Wang Han, Ning Wu, Fang Zhou, Fen Ge:
Reconfigurable Multi-algorithm Neural Network Accelerator Based on Target Detection. ICCT 2022: 1555-1559 - [c21]Shuning Wu, Fen Ge, Yi Zhang:
A Vehicle Line-Pressing Detection Approach Based on YOLOv5 and DeepSort. ICCT 2022: 1745-1749 - 2021
- [j20]Lili Shen, Ning Wu, Gaizhen Yan, Fen Ge:
Collaborative thermal- and traffic-aware adaptive routing scheme for 3D network-on-chip systems. IEICE Electron. Express 18(4): 20200425 (2021) - [j19]Fang Zhou, Caixian Fei, Ning Wu, Fen Ge:
Highly efficient architecture of elliptic curve scalar multiplication with fault tolerance over GF(2m). IEICE Electron. Express 18(11): 20210160 (2021) - [c20]Jin Wen, Ning Wu, Fen Ge, Fang Zhou, Zhixiang Xu, Benjun Zhang:
An Anti-DPA Elliptic Curve Cryptography Scalar Multiplier with Randomized Base Point. ICCT 2021: 100-104 - [c19]Tong Lu, Fang Zhou, Ning Wu, Fen Ge, Benjun Zhang:
Hardware Trojan Detection Method for Gate-Level Netlists Based on the Idea of Few-Shot Learning. ICCT 2021: 301-305 - [c18]Chenchen Cui, Fen Ge, Ziyu Li, Xin Yue, Fang Zhou, Ning Wu:
Design and Implementation of OpenCL-Based FPGA Accelerator for YOLOv2. ICCT 2021: 1004-1007 - [c17]Ying Yang, Fen Ge, Danfeng Qiu, Xin Yue, Ziyu Li, Fang Zhou, Ning Wu:
Implementation of Reconfigurable CNN-LSTM Accelerator Based on FPGA. ICCT 2021: 1026-1030 - 2020
- [j18]Lei Zhang, Ning Wu, Fen Ge, Fang Zhou, Mahammad Rehan Yahya:
A Dynamic Branch Predictor Based on Parallel Structure of SRNN. IEEE Access 8: 86230-86237 (2020) - [j17]Wentao Xu, Ning Wu, Fen Ge:
Minimizing the number of wavelengths in a cluster WDM mesh-based ONoC through application-specific mapping. IEICE Electron. Express 17(6): 20200045 (2020) - [j16]Hao Xiao, Yanming Fan, Fen Ge, Zhang Zhang, Xin Cheng:
Algorithm-Hardware Co-Design of Real-Time Edge Detection for Deep-Space Autonomous Optical Navigation. IEICE Trans. Inf. Syst. 103-D(10): 2047-2058 (2020) - [c16]Liangkai Zhao, Ning Wu, Fen Ge, Fang Zhou, Jiahui Zhang, Tong Lu:
Small Area Configurable Deep Neural Network Accelerator for IoT System. ICCT 2020: 795-799 - [c15]Yayue Zhao, Fen Ge, Chenchen Cui, Fang Zhou, Ning Wu:
A Mapping Method for Convolutional Neural Networks on Network-on-Chip. ICCT 2020: 916-920 - [c14]Liang Han, Ning Wu, Fen Ge, Fang Zhou, Jin Wen, Peiyao Qing:
Differential Fault Attack for the Iterative Operation of AES-192 Key Expansion. ICCT 2020: 1156-1160 - [c13]Caixian Fei, Fang Zhou, Ning Wu, Fen Ge, Jin Wen, Peiyao Qin:
A Scalable Bit-Parallel Word-Serial Multiplier with Fault Detection on GF(2^m). ICCT 2020: 1660-1664 - [c12]Weifeng Zhang, Fen Ge, Chenchen Cui, Ying Yang, Fang Zhou, Ning Wu:
Design and Implementation of LSTM Accelerator Based on FPGA. ICCT 2020: 1675-1679
2010 – 2019
- 2019
- [j15]Yafei Zhang, Ning Wu, Gaizhen Yan, Fen Ge:
Machine learning-based dynamic reconfiguration algorithm for reconfigurable NoCs. IEICE Electron. Express 16(2): 20181040 (2019) - [j14]Qiangjia Bi, Ning Wu, Fang Zhou, Jinbao Zhang, Muhammad Rehan Yahya, Fen Ge:
Fault attack hardware Trojan detection method based on ring oscillator. IEICE Electron. Express 16(8): 20190143 (2019) - [j13]Muhammad Rehan Yahya, Ning Wu, Gaizhen Yan, Fen Ge, Tanveer Ahmed:
RoR: A low insertion loss design of rearrangeable hybrid photonic-plasmonic 6 × 6 non-blocking router for ONoCs. IEICE Electron. Express 16(13): 20190346 (2019) - [c11]Xiangli Li, Fen Ge, Ben Rui, Ning Wu, Fang Zhou:
A dual-threshold credit-based flow control mechanism for 3D Network-on-Chip. ICICDT 2019: 1-4 - [c10]Xinhao Shi, Ning Wu, Fen Ge, Gaizhen Yan, Yan Xing, Xudong Ma:
Srax: A Low Crosstalk and Insertion Loss 5×5 Optical Router for Optical Network-on-Chip. IECON 2019: 3102-3105 - 2018
- [j12]Jinbao Zhang, Ning Wu, Fen Ge, Fang Zhou, Xiaoqing Zhang:
Countermeasure against fault sensitivity analysis based on clock check block. IEICE Electron. Express 15(11): 20180433 (2018) - 2017
- [j11]Gaizhen Yan, Ning Wu, Fen Ge, Hao Xiao, Fang Zhou:
ArR-DTM: A routing-based DTM for 3D NoCs by adaptive degree regulation. IEICE Electron. Express 14(9): 20170203 (2017) - [j10]Lili Shen, Ning Wu, Gaizhen Yan, Fen Ge:
Thermal-aware task mapping for communication energy minimization on 3D NoC. IEICE Electron. Express 14(22): 20170900 (2017) - [j9]Gaizhen Yan, Ning Wu, Fen Ge, Hao Xiao, Fang Zhou:
Collaborative fuzzy-based partially-throttling dynamic thermal management scheme for three-dimensional networks-on-chip. IET Comput. Digit. Tech. 11(1): 24-32 (2017) - 2016
- [j8]Hao Xiao, Huajuan Zhang, Fen Ge, Ning Wu:
A MapReduce architecture for embedded multiprocessor system-on-chips. IEICE Electron. Express 13(2): 20151025 (2016) - [j7]Gui Feng, Fen Ge, Ning Wu, Lei Zhou, Jing Liu:
MSP based thermal-aware mapping approach for 3D Network-on-Chip under performance constraints. IEICE Electron. Express 13(7): 20160082 (2016) - [j6]Xiaoqiang Zhang, Ning Wu, Fang Zhou, Fen Ge:
Optimization of Area and Delay for Implementation of the Composite Field Advanced Encryption Standard S-Box. J. Circuits Syst. Comput. 25(5): 1650037:1-1650037:29 (2016) - [j5]Hao Xiao, Ning Wu, Fen Ge, Tsuyoshi Isshiki, Hiroaki Kunieda, Jun Xu, Yuangang Wang:
Efficient Synchronization for Distributed Embedded Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 779-783 (2016) - [j4]Jia Zhan, Jin Ouyang, Fen Ge, Jishen Zhao, Yuan Xie:
Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC. IEEE Trans. Very Large Scale Integr. Syst. 24(10): 3041-3054 (2016) - 2015
- [j3]Jintao Zheng, Ning Wu, Gaizhen Yan, Fen Ge, Lei Zhou:
Dynamically reconfigurable simulation platform for 3D NoC based on multi-FPGA. IEICE Electron. Express 12(7): 20150065 (2015) - [j2]Zhiping Wu, Ning Wu, Lei Zhou, Fen Ge:
The Adaptive Thermal and Traffic-Balanced Routing algorithm based on temperature analysis and traffic statistics. IEICE Electron. Express 12(7): 20150101 (2015) - [j1]Hao Xiao, Ning Wu, Fen Ge, Guanyu Zhu, Lei Zhou:
Distributed Synchronization for Message-Passing Based Embedded Multiprocessors. IEICE Trans. Inf. Syst. 98-D(2): 272-275 (2015) - [c9]RongRong Zhou, Fen Ge, Gui Feng, Ning Wu:
A network components insertion method for 3D application-specific Network-on-Chip. ASICON 2015: 1-4 - [c8]Jia Zhan, Jin Ouyang, Fen Ge, Jishen Zhao, Yuan Xie:
DimNoC: a dim silicon approach towards power-efficient on-chip network. DAC 2015: 10:1-10:6 - [c7]Fen Ge, Jia Zhan, Yuan Xie, Vijaykrishnan Narayanan:
Exploring memory controller configurations for many-core systems with 3D stacked DRAMs. ISQED 2015: 565-570 - 2014
- [c6]Qiaosha Zou, Jia Zhan, Fen Ge, Matt Poremba, Yuan Xie:
Designing vertical bandwidth reconfigurable 3D NoCs for many core systems. 3DIC 2014: 1-7 - 2013
- [c5]Gui Feng, Fen Ge, Shuang Yu, Ning Wu:
A thermal-aware mapping algorithm for 3D Mesh Network-on-Chip architecture. ASICON 2013: 1-4 - [c4]Shuang Yu, Fen Ge, Gui Feng, Ning Wu:
A two-phase floorplanning approach for Application-specific Network-on-Chip. ASICON 2013: 1-4 - 2012
- [c3]Ying Zhang, Ning Wu, Xiazhi Ke, Fen Ge:
A Coverage-Driven Verification Platform for Evaluating NoC Performance and Test Structure. AINA Workshops 2012: 261-265
2000 – 2009
- 2009
- [c2]Ning Wu, Fen Ge, Fei Wu:
Design of a GALS Wrapper for Network on Chip. CSIE (3) 2009: 592-595 - 2008
- [c1]Fen Ge, Ning Wu:
A minimum-path mapping algorithm for 2D mesh Network on Chip architecture. APCCAS 2008: 1542-1545
Coauthor Index
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