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ORCIDKathy Wilcox
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- affiliation: AMD, Boxborough, MA, USA
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2020 – today
- 2023
[c11]Benjamin Munger, Kathy Wilcox, Jeshuah Sniderman, Chuck Tung, Brett Johnson, Russell Schreiber, Carson Henrion, Kevin Gillespie, Tom Burd, Harry R. Fair III, Dave Johnson, Jonathan White, Scott McLelland, Steven Bakke, Javin Olson, Ryan McCracken, Matthew Pickett, Aaron Horiuchi, Hien Nguyen, Tim Jackson:
"Zen 4": The AMD 5nm 5.7GHz x86-64 Microprocessor Core. ISSCC 2023: 38-39- 2021
- [c10]Alicia Klinefelter, Huichu Liu, Luca Benini, Yvain Thonnart, Keith A. Bowman, Kathy Wilcox, David Bol, Alvin Loke, Ofer Shacham:
SE2: Going Remote: Challenges and Opportunities to Remote Learning, Work, and Collaboration. ISSCC 2021: 539-540 - [c9]Negar Reiskarimian
, Zeynep Toprak Deniz, Ulkuhan Guler, Kathy Wilcox, Alice Wang, Jane Gu, Yaoyao Jia, Alicia Klinefelter, Rikky Muller, Farhana Sheikh, Yildiz Sinangil, Trudy Stetzler, Vivienne Sze, Rabia Tugce Yazicigil, Deeksha Lal, Dina El-Damak:
SE4: ICs in PandemICs. ISSCC 2021: 543-545
2010 – 2019
- 2017
- [c8]Kathy Wilcox, Youngmin Shin, Edith Beigné:
Session 26 overview: Processor-power management and clocking. ISSCC 2017: 436-437 - 2016
- [j2]Benjamin Munger, David Akeson, Srikanth Arekapudi, Tom Burd, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White, Kathryn Wilcox:
Carrizo: A High Performance, Energy Efficient 28 nm APU. IEEE J. Solid State Circuits 51(1): 105-116 (2016) - [c7]John Maneatis, Kathy Wilcox:
Session 19 overview: Digital PLLs. ISSCC 2016: 322-323 - 2015
- [j1]Kathryn Wilcox, Robert Cole, Harry R. Fair III, Kevin Gillespie, Aaron Grenat, Carson Henrion, Ravi Jotwani, Stephen Kosonocky, Benjamin Munger, Samuel Naffziger, Robert S. Orefice, Sanjay Pant, Donald A. Priore, Ravinder Rachala, Jonathan White:
Steamroller Module and Adaptive Clocking System in 28 nm CMOS. IEEE J. Solid State Circuits 50(1): 24-34 (2015) - [c6]Bing Sheu, Kathy Wilcox, Ali M. Keshavarzi, Dimitri A. Antoniadis:
EP1: Moore's law challenges below 10nm: Technology, design and economic implications. ISSCC 2015: 1 - [c5]Marian Verhelst, Dennis Sylvester, Makoto Takamiya, Mike Clinton, Kathy Wilcox, Koichi Nose:
F4: Building the Internet of Everything (IoE): Low-power techniques at the circuit and system levels. ISSCC 2015: 1-2 - [c4]Kathryn Wilcox, David Akeson, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White:
4.8 A 28nm x86 APU optimized for power and area efficiency. ISSCC 2015: 1-3 - 2014
- [c3]Kevin Gillespie, Harry R. Fair III, Carson Henrion, Ravi Jotwani, Stephen V. Kosonocky, Robert S. Orefice, Donald A. Priore, Jonathan White, Kathryn Wilcox:
5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS. ISSCC 2014: 104-105 - 2011
- [c2]Tim C. Fischer, Srikanth Arekapudi, Eric Busta, Carl Dietz, Michael Golden, Scott Hilker, Aaron Horiuchi, Kevin A. Hurd, Dave Johnson, Hugh McIntyre, Samuel Naffziger, James Vinh, Jonathan White, Kathryn Wilcox:
Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU. ISSCC 2011: 78-80
1990 – 1999
- 1998
- [c1]Mark Matson, Dan Bailey, Shane L. Bell, Larry L. Biro, Steve Butler, John Clouser, Jim Farrell, Mike Gowan, Donald A. Priore, Kathryn Wilcox:
Circuit implementation of a 600 MHz superscalar RISC microprocessor. ICCD 1998: 104-110
Coauthor Index
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