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2020 – today
- 2023
[c11]Pranose J. Edavoor
, Aneesh Raveendran, David Selvakumar, Vivian Desalphine, Shankar G. Dharani, Gopal Raut:
Design and Analysis of Posit Quire Processing Engine for Neural Network Applications. VLSID 2023: 252-257- 2021
- [c10]Venkata Reddy Kolagatla, Vivian Desalphine, David Selvakumar:
Area-Time Scalable High Radix Montgomery Modular Multiplier for Large Modulus. VDAT 2021: 1-4 - [c9]David Selvakumar, J. Mervin, Shashikala Gunderao Pattanshetty, Vivian Desalphine:
Formal Verification and Analysis of a Pseudo Random Number Generator. VDAT 2021: 1-6 - [c8]Annarao Kulkarni, Shashikala Gunderao Pattanshetty, Aneesh Raveendran, David Selvakumar, Sandra Jean, Vivian Desalphine:
PositGen-A Verification Suite for Posit Arithmetic. VLSID 2021: 204-209 - [c7]Sandra Jean, Aneesh Raveendran, A. David Selvakumar, Gagandeep Kaur, Shankar G. Dharani, Shashikala Gunderao Pattanshetty, Vivian Desalphine:
P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor. VLSID 2021: 282-287 - 2020
- [c6]Vivian Desalphine, Somya Dashora, Laxita Mali, Suhas K, Aneesh Raveendran, David Selvakumar:
Novel Method for Verification and Performance Evaluation of a Non-Blocking Level-1 Instruction Cache designed for Out-of-Order RISC-V Superscaler Processor on FPGA. VDAT 2020: 1-4 - [c5]Aneesh Raveendran, Sandra Jean, J. Mervin, Vivian Desalphine, David Selvakumar:
A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture. VLSID 2020: 207-212
2010 – 2019
- 2019
- [c4]Aneesh Raveendran, Sandra Jean, J. Mervin, Vivian Desalphine, A. David Selvakumar:
RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor. VDAT 2019: 482-495 - [c3]Aneesh Raveendran, Vinay Kumar, Vivian Desalphine, David Selvakumar:
Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU. VDAT 2019: 496-509 - 2015
- [c2]Vinayak Patil, Aneesh Raveendran, P. M. Sobha, A. David Selvakumar, Vivian Desalphine:
Out of order floating point coprocessor for RISC V ISA. VDAT 2015: 1-7 - [c1]Aneesh Raveendran, Vinayak Patil, Vivian Desalphine, P. M. Sobha, A. David Selvakumar:
RISC-V out-of-order data conversion co-processor. VDAT 2015: 1-2
Coauthor Index
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