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2020 – today
- 2024
[i4]José L. Risco-Martín, Saurabh Mittal, Juan Carlos Fabero Jiménez, Marina Zapater, Román Hermida:
Reconsidering the performance of DEVS modeling and simulation environments using the DEVStone benchmark. CoRR abs/2402.05483 (2024)- 2023
- [i3]Kevin Henares, José L. Risco-Martín, José L. Ayala, Román Hermida:
Efficient micro data centres deployment for mobile healthcare monitoring systems in IoT urban scenarios. CoRR abs/2302.10201 (2023) - 2022
- [j38]Kevin Henares
, José L. Risco-Martín, José L. Ayala, Román Hermida:
Efficient micro data centres deployment for mobile healthcare monitoring systems in IoT urban scenarios. J. Simulation 16(6): 589-603 (2022) - [i2]Marina Zapater, José L. Risco-Martín, Patricia Arroba, José L. Ayala, José Manuel Moya, Román Hermida:
Runtime data center temperature prediction using Grammatical Evolution techniques. CoRR abs/2211.06329 (2022) - 2020
- [j37]Jose Manuel Bote, Joaquín Recas, Román Hermida:
Evaluation of blood pressure estimation models based on pulse arrival time. Comput. Electr. Eng. 84: 106616 (2020)
2010 – 2019
- 2019
- [j36]Min Soo Kim, Alberto A. Del Barrio, Leonardo Tavares Oliveira, Román Hermida, Nader Bagherzadeh:
Efficient Mitchell's Approximate Log Multipliers for Convolutional Neural Networks. IEEE Trans. Computers 68(5): 660-675 (2019) - [j35]Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik:
A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Datapaths. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(2): 742-755 (2019) - [c59]Kevin Henares, José L. Risco-Martín, Román Hermida, Gemma Reig Roselló, Román Cárdenas:
Modular framework to model critical events in stroke patients. SummerSim 2019: 48:1-48:12 - 2018
- [j34]David Guillermo Fernández, Alberto A. Del Barrio, Guillermo Botella Juan, Carlos García, Manuel Prieto, Román Hermida:
Complexity reduction in the HEVC/H265 standard based on smooth region classification. Digit. Signal Process. 73: 24-39 (2018) - [j33]Jose Manuel Bote, Joaquín Recas, Francisco J. Rincón, David Atienza, Román Hermida:
A Modular Low-Complexity ECG Delineation Algorithm for Real-Time Embedded Systems. IEEE J. Biomed. Health Informatics 22(2): 429-441 (2018) - [c58]Min Soo Kim, Alberto A. Del Barrio, Román Hermida, Nader Bagherzadeh:
Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks. ASP-DAC 2018: 617-622 - 2017
- [j32]José L. Risco-Martín, Saurabh Mittal, Juan Carlos Fabero Jiménez, Marina Zapater, Román Hermida:
Reconsidering the performance of DEVS modeling and simulation environments using the DEVStone benchmark. Simul. 93(6): 459-476 (2017) - [c57]Alberto A. Del Barrio, Román Hermida:
A slack-based approach to efficiently deploy radix 8 booth multipliers. DATE 2017: 1153-1158 - 2016
- [j31]Marina Zapater, José L. Risco-Martín, Patricia Arroba, José L. Ayala, José Manuel Moya, Román Hermida:
Runtime data center temperature prediction using Grammatical Evolution techniques. Appl. Soft Comput. 49: 94-107 (2016) - [j30]Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik:
A Partial Carry-Save On-the-Fly Correction Multispeculative Multiplier. IEEE Trans. Computers 65(11): 3251-3264 (2016) - [j29]Alberto A. Del Barrio, Jason Cong, Román Hermida:
A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3): 419-432 (2016) - 2014
- [j28]Joaquín Recas, Nadia Khaled, Alberto A. Del Barrio, Román Hermida:
Generic Markov model of the contention access period of IEEE 802.15.4 MAC layer. Digit. Signal Process. 33: 191-205 (2014) - [j27]Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik, Jose Manuel Mendias, María C. Molina:
Improving circuit performance with multispeculative additive trees in high-level synthesis. Microelectron. J. 45(11): 1470-1479 (2014) - [j26]Alberto A. Del Barrio, Nader Bagherzadeh, Román Hermida:
Ultra-low-power adder stage design for exascale floating point units. ACM Trans. Embed. Comput. Syst. 13(3s): 105:1-105:24 (2014) - 2013
- [j25]Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, José M. Mendías, Román Hermida:
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths. Integr. 46(2): 119-130 (2013) - [j24]José Luis Imaña, Román Hermida, Francisco Tirado:
Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials. Integr. 46(2): 197-210 (2013) - [c56]Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik, Jose Manuel Mendias, María C. Molina:
Multispeculative additive trees in high-level synthesis. DATE 2013: 188-193 - [c55]Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik:
Exploring the energy efficiency of Multispeculative Adders. ICCD 2013: 309-315 - 2012
- [j23]Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik, José M. Mendías, María C. Molina:
Multispeculative Addition Applied to Datapath Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1817-1830 (2012) - 2011
- [j22]Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, Jose Manuel Mendias, Román Hermida:
A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 350-363 (2011) - [c54]Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, José M. Mendías, Román Hermida:
Power optimization in heterogenous datapaths. DATE 2011: 1400-1405 - 2010
- [c53]Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Román Hermida, Seda Ogrenci Memik:
Using Speculative Functional Units in high level synthesis. DATE 2010: 1779-1784
2000 – 2009
- 2009
- [j21]Marcos Sánchez-Élez, Nader Bagherzadeh, Román Hermida:
A framework for low energy data management in reconfigurable multi-context architectures. J. Syst. Archit. 55(2): 127-139 (2009) - [j20]María C. Molina, Rafael Ruiz-Sautua, Pedro Garcia-Repetto, Román Hermida:
Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1): 60-73 (2009) - 2008
- [j19]Fredy Rivera, Marcos Sánchez-Élez, Román Hermida, Nader Bagherzadeh:
Scheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures. IET Comput. Digit. Tech. 2(3): 199-213 (2008) - [c52]Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida:
Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis. DSD 2008: 267-273 - [c51]Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida, Francisco Tirado:
Applying speculation techniques to implement functional units. ICCD 2008: 74-80 - 2007
- [j18]David Atienza, Pablo García Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida:
HW-SW emulation framework for temperature-aware design in MPSoCs. ACM Trans. Design Autom. Electr. Syst. 12(3): 26:1-26:26 (2007) - [c50]María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida:
Area optimization of multi-cycle operators in high-level synthesis. DATE 2007: 449-454 - [i1]Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida:
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis. CoRR abs/0710.4801 (2007) - 2006
- [j17]María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida:
Bitwise scheduling to balance the computational cost of behavioral specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(1): 31-46 (2006) - [j16]José Luis Imaña, Román Hermida, Francisco Tirado:
Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials. IEEE Trans. Very Large Scale Integr. Syst. 14(12): 1388-1393 (2006) - [c49]Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida:
Pre-synthesis optimization of multiplications to improve circuit performance. DATE 2006: 1306-1311 - [c48]Fredy Rivera, Marcos Sánchez-Élez, Milagros Fernández, Román Hermida, Nader Bagherzadeh:
Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures. FPL 2006: 1-8 - 2005
- [c47]Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida:
Arrival time aware scheduling to minimize clock cycle length. ASP-DAC 2005: 1018-1021 - [c46]Nicolas Genko, David Atienza, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, Francky Catthoor:
A Complete Network-On-Chip Emulation Framework. DATE 2005: 246-251 - [c45]Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida:
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis. DATE 2005: 1252-1257 - [c44]Rafael Ruiz-Sautua, María C. Molina, Jose Manuel Mendias, Román Hermida:
Performance-driven read-after-write dependencies softening in high-level synthesis. ICCAD 2005: 7-12 - [c43]Fredy Rivera, Marcos Sánchez-Élez, Milagros Fernández, Román Hermida, Nader Bagherzadeh:
Low Power Data Prefetch for 3D Image Applications on Coarse-Grain Reconfigurable Architectures. IPDPS 2005 - [c42]Nicolas Genko, David Atienza, Giovanni De Micheli, Luca Benini, Jose Manuel Mendias, Román Hermida, Francky Catthoor:
A novel approach for network on chip emulation. ISCAS (3) 2005: 2365-2368 - [c41]J. B. Pérez-Ramas, David Atienza, Miguel Peón Quirós, Ivan Magan, Jose Manuel Mendias, Román Hermida:
Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs. PARCO 2005: 769-776 - 2004
- [j15]Juan de Vicente, Juan Lanchares, Román Hermida:
Annealing placement by thermodynamic combinatorial optimization. ACM Trans. Design Autom. Electr. Syst. 9(3): 310-332 (2004) - [c40]Fredy Rivera, Marcos Sánchez-Élez, Milagros Fernández, Román Hermida, Nader Bagherzadeh:
Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures. CODES+ISSS 2004: 30-35 - [c39]María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida:
Behavioural Bitwise Scheduling Based on Computational Effort Balancing. DATE 2004: 684-685 - [c38]María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida:
Behavioural Scheduling to Balance the Bit-Level Computational Effort. ISVLSI 2004: 99-104 - [c37]José Manuel Colmenar, Oscar Garnica, Sonia López, José Ignacio Hidalgo, Juan Lanchares, Román Hermida:
Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays. PDP 2004: 112-119 - 2003
- [j14]María C. Molina, José M. Mendías, Román Hermida:
Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources. J. Syst. Archit. 49(12-15): 505-519 (2003) - [c36]Marcos Sánchez-Élez, Milagros Fernández, Manuel L. Anido, Haitao Du, Nader Bagherzadeh, Román Hermida:
Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures. DATE 2003: 10036-10043 - [c35]María C. Molina, José M. Mendías, Román Hermida:
High-Level Allocation to Minimize Internal Hardware Wastage. DATE 2003: 10264-10269 - [c34]José Ignacio Hidalgo, Francisco Fernández, Juan Lanchares, Juan Manuel Sánchez-Pérez, Román Hermida, Marco Tomassini, Ranieri Baraglia, Raffaele Perego, Oscar Garnica:
Multi-FPGA Systems Synthesis by Means of Evolutionary Computation. GECCO 2003: 2109-2120 - [c33]Sonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida:
Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization. PATMOS 2003: 151-160 - [c32]María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida:
Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis. PATMOS 2003: 617-627 - 2002
- [j13]Oscar Garnica, Juan Lanchares, Román Hermida:
Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. Fundam. Informaticae 50(2): 155-174 (2002) - [j12]José M. Mendías, Román Hermida, Olga Peñalba:
A study about the efficiency of formal high-level synthesis applied to verification. Integr. 31(2): 101-131 (2002) - [j11]Olga Peñalba, José M. Mendías, Román Hermida:
A global approach to improve conditional hardware reuse in high-level synthesis. J. Syst. Archit. 47(12): 959-975 (2002) - [c31]María C. Molina, José M. Mendías, Román Hermida:
High-level synthesis of multiple-precision circuitsindependent of data-objects length. DAC 2002: 612-615 - [c30]Juan de Vicente, Juan Lanchares, Román Hermida:
FPGA Placement by Thermodynamic Combinatorial Optimization. DATE 2002: 54-60 - [c29]Marcos Sánchez-Élez, Milagros Fernández, Rafael Maestre, Román Hermida, Nader Bagherzadeh, Fadi J. Kurdahi:
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures. DATE 2002: 547-552 - [c28]María C. Molina, José M. Mendías, Román Hermida:
Multiple-Precision Circuits Allocation Independent of Data-Objects Length. DATE 2002: 909-913 - [c27]Olga Peñalba, José M. Mendías, Román Hermida:
Maximizing Conditonal Reuse by Pre-Synthesis Transformations. DATE 2002: 1097 - [c26]José Ignacio Hidalgo, Juan Lanchares, Aitor Ibarra, Román Hermida:
A Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design. DSD 2002: 60-69 - [c25]Aitor Ibarra, José M. Mendías, Juan Lanchares, José Ignacio Hidalgo, Román Hermida:
Optimization of Equational Specifications Using Genetic Techniques. DSD 2002: 252-258 - [c24]José M. Mendías, Román Hermida, María C. Molina, Olga Peñalba:
Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis. DSD 2002: 308-315 - [c23]Olga Peñalba, José M. Mendías, Román Hermida:
Source Code Transformation to Improve Conditional Hardware Reuse. DSD 2002: 324-331 - [c22]María C. Molina, José M. Mendías, Román Hermida:
Bit-Level Allocation of Multiple-Precision Specifications. DSD 2002: 385-392 - [c21]Aitor Ibarra, Juan Lanchares, Jose Manuel Mendias, José Ignacio Hidalgo, Román Hermida:
Transformation of Equational Specification by Means of Genetic Programming. EuroGP 2002: 248-257 - [c20]María C. Molina, José M. Mendías, Román Hermida:
Bit-level scheduling of heterogeneous behavioural specifications. ICCAD 2002: 602-608 - [c19]Oscar Garnica, Juan Lanchares, Román Hermida:
A New Methodology to Design Low-Power Asynchronous Circuits. PATMOS 2002: 108-117 - 2001
- [j10]Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh:
Kernel scheduling techniques for efficient solution space exploration in reconfigurable computing. J. Syst. Archit. 47(3-4): 277-292 (2001) - [j9]Rafael Maestre, F. Kurdahl, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh:
A formal approach to context scheduling for multicontext reconfigurable architectures. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 173-185 (2001) - [j8]Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh:
A framework for reconfigurable computing: task scheduling and context management. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 858-873 (2001) - [c18]Oscar Garnica, Juan Lanchares, Román Hermida:
Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. ACSD 2001: 167-178 - [c17]Oscar Garnica, Juan Lanchares, Román Hermida:
A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits. DATE 2001: 810 - [c16]Marcos Sánchez-Élez, Milagros Fernández, Román Hermida, Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh:
A data scheduler for multi-context reconfigurable architectures. ISSS 2001: 177-182 - [e2]Román Hermida, El Mostapha Aboulhamid:
Proceedings of the 14th International Symposium on Systems Synthesis, ISSS 2001, Montrél, Québec, Canada, September 30 - October 3, 2001. ACM / IEEE Computer Society 2001, ISBN 1-58113-418-5 [contents] - 2000
- [c15]José Ignacio Hidalgo, Juan Lanchares, Román Hermida:
Partitioning and Placement for Multi-FPGA Systems Using Genetic Algorithms. EUROMICRO 2000: 1204-1211 - [c14]Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh:
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. FCCM 2000: 297-298 - [c13]Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh:
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. ICCD 2000: 575-576 - [c12]Juan de Vicente, Juan Lanchares, Román Hermida:
Adaptive FPGA Placement by Natural Optimization. IEEE International Workshop on Rapid System Prototyping 2000: 188-193 - [e1]Fadi J. Kurdahi, Román Hermida:
Proceedings of the 13th International Symposium on System Synthesis, ISSS'00, Madrid, Spain, September 20-22, 2000. ACM / IEEE Computer Society 2000, ISBN 0-7695-0765-4 [contents]
1990 – 1999
- 1999
- [c11]Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh, Román Hermida, Milagros Fernández:
Kernel Scheduling in Reconfigurable Computing. DATE 1999: 90-96 - [c10]Juan Antonio Maestro, Daniel Mozos, Román Hermida:
The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach. DATE 1999: 766-767 - [c9]Olga Peñalba, José M. Mendías, Román Hermida:
A Unified Algorithm for Mutual Exclusiveness Identification. EUROMICRO 1999: 1504-1510 - [c8]Juan de Vicente, Juan Lanchares, Román Hermida:
Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies. FPL 1999: 91-100 - [c7]Rafael Maestre, Milagros Fernández, Román Hermida, Nader Bagherzadeh:
A Framework for Scheduling and Context Allocation in Reconfigurable Computing. ISSS 1999: 134-140 - 1998
- [c6]José M. Mendías, Román Hermida:
Correct High-Level Synthesis: a Formal Perspective. DATE 1998: 977-978 - [c5]Juan de Vicente, Juan Lanchares, Román Hermida:
RSR: A New Rectilinear Steiner Minimum Tree Approximation for FPGA Placement and Global Routing. EUROMICRO 1998: 10192-10195 - 1997
- [j7]R. Moreno, Román Hermida, Milagros Fernández, Hortensia Mecha:
A unified approach for scheduling and allocation. Integr. 23(1): 1-35 (1997) - [c4]José M. Mendías, Román Hermida, Milagros Fernández:
Formal Techniques for Hardware Allocation. VLSI Design 1997: 161-165 - 1996
- [j6]R. Moreno, Román Hermida, Milagros Fernández:
Register estimation in unscheduled dataflow graphs. ACM Trans. Design Autom. Electr. Syst. 1(3): 396-403 (1996) - [c3]José M. Mendías, Román Hermida, Milagros Fernández:
Algebraic Support for Transformational Hardware Allocation. ED&TC 1996: 601 - 1994
- [j5]Hortensia Mecha, Milagros Fernández, Román Hermida, Daniel Mozos, Katzalin Olcoz:
Clock cycle estimation based on dead time and control unit area minimization. Microprocess. Microprogramming 40(10-12): 821-824 (1994) - 1993
- [j4]R. Moreno, Román Hermida, Daniel Mozos, Katzalin Olcoz:
Global hardware synthesis guided by realistic probability computation. Microprocess. Microprogramming 39(2-5): 233-236 (1993) - [c2]Román Hermida, Milagros Fernández, Francisco Tirado, Victor Manuel Sanchez, Pablo Ruperez:
An approach to module binding by fuzzy partitioning. EURO-DAC 1993: 58-63 - 1992
- [j3]Daniel Mozos, Julio Septién, Francisco Tirado, Román Hermida:
Design control in a high level synthesis system. Microprocess. Microprogramming 34(1-5): 93-96 (1992) - [c1]Julio Septién, Daniel Mozos, Francisco Tirado, Román Hermida, Milagros Fernández:
Heuristics for branch-and-bound global allocation. EURO-DAC 1992: 334-340 - 1991
- [j2]J. Septiéna, Daniel Mozos, Román Hermida, Francisco Tirado:
A hardware allocator guided by cost functions. Microprocessing and Microprogramming 32(1-5): 185-192 (1991) - 1990
- [j1]Alfonso Sotelo, Julio Septién, Román Hermida, Milagros Fernández:
An approach to minimal-time scheduling of micro-operations. Microprocessing and Microprogramming 28(1-5): 301-304 (1990)
Coauthor Index
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