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ORCIDRajasekhar Nagulapalli
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2020 – today
- 2024
[c16]Rakesh Kumar Palani, Srishti Agrawal, Ayan Alam Khan, Aadarsh V, Rajasekhar Nagulapalli:
A Wide Range Constant Transconductance Circuit Based on Negative Feedback for Analog Circuits. ISCAS 2024: 1-4- 2023
- [j12]Ravi Kumar, Rajasekhar Nagulapalli, Santosh Kumar Vishvakarma
:
A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency. J. Circuits Syst. Comput. 32(4): 2350059:1-2350059:10 (2023) - [c15]Rakesh Kumar Palani, Rajasekhar Nagulapalli, Srikar Bhagavatula:
Dynamic Averager Based Sub-1V Bandgap Voltage Reference. MWSCAS 2023: 890-894 - 2022
- [c14]Rajasekhar Nagulapalli, Khaled Hayatleh, Nabil Yassine, S. Barker:
A Novel Sub-1V Bandgap Reference with 17.1 ppm/0C Temperature coefficient in 28nm CMOS. ISCAS 2022: 1914-1917 - 2021
- [j11]Rajasekhar Nagulapalli, Rakesh Kumar Palani, Srikar Bhagavatula:
A 24.4 ppm/°C Voltage Mode Bandgap Reference With a 1.05V Supply. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1088-1092 (2021) - [c13]Rajasekhar Nagulapalli, Rakesh Kumar Palani, Sweta Agarwal, Shouri Chatterjee, K. Hayatleh, S. Barker:
A 15uW, 12 ppm/°C Curvature Compensated Bandgap in 0.85V Supply. ISCAS 2021: 1-4 - [c12]P. Mishra, A. Tan, Belal Helal, Cheng-Ru Ho, C. Loi, Jamal Riani, J. Sun, Kaizad Mistry, Karthik Raviprakash, L. Tse, M. Davoodi, M. Takefman, N. Fan, P. Prabha, Q. Liu, Q. Wang, Rajasekhar Nagulapalli, S. Cyrusian, S. Jantzi, S. Scouten, T. Dusatko, T. Setya, V. Giridharan, V. Gurumoorthy, Victor Karam, W. Liew, Y. Liao, Y. Ou:
8.7 A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET. ISSCC 2021: 138-140 - [c11]Rajasekhar Nagulapalli, Rakesh Kumar Palani:
A Novel 22.7 ppm/0C Voltage mode Sub-Bandgap Reference with robust startup nature. MWSCAS 2021: 844-847 - [c10]T. R. Varun, Rajasekhar Nagulapalli, Immanuel Raja:
A 82μW Mixed-Mode sub-1V Bandgap reference with 25 ppm/°C Temperature Co-efficient with Simultaneous PTAT Generation. VDAT 2021: 1-4 - 2020
- [j10]Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Amr A. Tammam, F. John Lidgey, Nabil Yassine:
A High-Sensitivity and Low-Power Circuit for the Measurement of Abnormal Blood Cell Levels. J. Circuits Syst. Comput. 29(4): 2050061:1-2050061:14 (2020) - [j9]Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker:
A VGA Linearity Improvement Technique for ECG Analog Front-End in 65nm CMOS. J. Circuits Syst. Comput. 29(7): 2050113:1-2050113:11 (2020) - [j8]Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker:
A Positive Feedback-Based Op-Amp Gain Enhancement Technique for High-Precision Applications. J. Circuits Syst. Comput. 29(14): 2050220:1-2050220:12 (2020) - [c9]Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, B. Naresh Kumar Reddy:
A Single BJT 10.2 ppm/°C Bandgap Reference in 45nm CMOS Technology. ICCCNT 2020: 1-4 - [c8]Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, B. Naresh Kumar Reddy:
A two-stage opamp frequency Compensation technique by splitting the 2nd stage. ICCCNT 2020: 1-5
2010 – 2019
- 2019
- [j7]Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Pantelis Georgiou, F. J. Lidgey:
A High Value, Linear and Tunable CMOS Pseudo-Resistor for Biomedical Applications. J. Circuits Syst. Comput. 28(6): 1950096:1-1950096:11 (2019) - [j6]Khaled Hayatleh, Saddam Zourob, Rajasekhar Nagulapalli, Steve Barker, Nabil Yassine, Pantelis Georgiou, F. J. Lidgey:
A High-Performance Skin Impedance Measurement Circuit for Biomedical Applications. J. Circuits Syst. Comput. 28(7): 1950110:1-1950110:15 (2019) - [j5]Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Amr A. Tammam, Pantelis Georgiou, F. J. Lidgey:
A 0.55 V Bandgap Reference with a 59 ppm/°C Temperature Coefficient. J. Circuits Syst. Comput. 28(7): 1950120:1-1950120:12 (2019) - [j4]Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Amr A. Tammam, Nabil Yassine, Bilal Yassine, Mohamed Ben-Esmael:
A Low Noise Amplifier Suitable for Biomedical Recording Analog Front-End in 65nm CMOS Technology. J. Circuits Syst. Comput. 28(8): 1950137:1-1950137:12 (2019) - [j3]Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Bilal Yassine, Saddam Zourob, Sumathi Raparthy, Nabil Yassine:
A Start-up Assisted Fully Differential Folded Cascode Opamp. J. Circuits Syst. Comput. 28(10): 1950164:1-1950164:12 (2019) - [j2]Rajasekhar Nagulapalli:
A CMOS Self-Bias CTAT Current Generator with Improved Supply Sensitivity. J. Circuits Syst. Comput. 28(13): 1950226:1-1950226:10 (2019) - [c7]Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, B. Naresh Kumar Reddy, B. Seetharamulu:
A Low Power Miller Compensation Technique for Two Stage Op-amp in 65nm CMOS Technology. ICCCNT 2019: 1-5 - [c6]Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, B. Naresh Kumar Reddy, B. Seetharamulu:
A High Frequency CMRR improvement technique for Differential Amplifiers in 45nm CMOS. ICCCNT 2019: 1-5 - 2018
- [j1]Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Sumathi Raparthy, Nabil Yassine, John Lidgey:
A 0.6 V MOS-Only Voltage Reference for Biomedical Applications with 40 ppm/∘C Temperature Drift. J. Circuits Syst. Comput. 27(8): 1850128:1-1850128:13 (2018) - [c5]Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Saddam Zourob, Nabil Yassine, B. Naresh Kumar Reddy:
A Technique to Reduce the Capacitor Size in Two Stage Miller Compensated Opamp. ICCCNT 2018: 1-4 - [c4]Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Saddam Zourob, Nabil Yassine, B. Naresh Kumar Reddy:
High Performance Circuit Techniques for Nueral Front-End Design in 65nm CMOS. ICCCNT 2018: 1-4 - [c3]Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Saddam Zourob, Nabil Yassine, B. Naresh Kumar Reddy:
A 31 ppm/° C Pure CMOS Bandgap Reference by Exploiting Beta-Multiplier. VDAT 2018: 100-108 - 2016
- [c2]Ahmed Awny, Rajasekhar Nagulapalli, Daniel Micusik, Jan Hoffmann, Gunter Fischer, Dietmar Kissinger, Ahmet Cagri Ulusoy:
23.5 A dual 64Gbaud 10kΩ 5% THD linear differential transimpedance amplifier with automatic gain control in 0.13µm BiCMOS technology for optical fiber coherent receivers. ISSCC 2016: 406-407 - 2010
- [c1]Kunal Desai, Rajasekhar Nagulapalli, Vijay Krishna, Rajkumar Palwai, Pravin Kumar Venkatesan, Vijay Khawshe:
High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique. VLSI Design 2010: 300-305
Coauthor Index
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