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Philippe Marquet

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2020 – today

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2022
[c36]
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Anne-Laure Ligozat, Kevin Marquet, Aurélie Bugeau, Julien Lefèvre, Pierre Boulet, Sylvain Bouveret, Philippe Marquet, Olivier Ridoux, Olivier Michel:
How to Integrate Environmental Challenges in Computing Curricula? SIGCSE (1) 2022: 899-905

2010 – 2019

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2019
[j9]
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Hana Krichene, Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid:
SCAC: Weakly-coupled execution model for massively parallel systems. Microprocess. Microsystems 64: 128-142 (2019)
2016
[c35]
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Hana Krichene, Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid:
SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively Parallel SoC. PDP 2016: 759-762
2015
[j8]
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Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid:
FPGA-based many-core System-on-Chip design. Microprocess. Microsystems 39(4-5): 302-312 (2015)
2013
[c34]
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Hana Krichene, Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser:
Master-Slave Control Structure for Massively Parallel System on Chip. DSD 2013: 917-924
2012
[j7]
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Rabie Ben Atitallah, Éric Piel, Smaïl Niar, Philippe Marquet, Jean-Luc Dekeyser:
A fast MPSoC virtual prototyping for intensive signal processing applications. Microprocess. Microsystems 36(3): 176-189 (2012)
[c33]
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Hana Krichene, Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser:
Broadcast with mask on a massively parallel processing on a chip. HPCS 2012: 275-280
2011
[j6]
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Abdoulaye Gamatié, Sébastien Le Beux, Éric Piel, Rabie Ben Atitallah, Anne Etien, Philippe Marquet, Jean-Luc Dekeyser:
A Model-Driven Design Framework for Massively Parallel Embedded Systems. ACM Trans. Embed. Comput. Syst. 10(4): 39:1-39:36 (2011)
[c32]
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Mouna Baklouti, Manel Ammar, Philippe Marquet, Mohamed Abid, Jean-Luc Dekeyser:
A model-driven based framework for rapid parallel SoC FPGA prototyping. International Symposium on Rapid System Prototyping 2011: 149-155
2010
[j5]
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Mouna Baklouti, Yassine Aydi, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid:
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA. J. Syst. Archit. 56(7): 278-292 (2010)
[c31]
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Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid:
Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip. ARC 2010: 110-121
[c30]
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Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser:
IP Based Configurable SIMD Massively Parallel SoC. FPL 2010: 247-250

2000 – 2009

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2009
[c29]
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Mouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser:
Study and integration of a parametric neighbouring interconnection network in a massively parallel architecture on FPGA. AICCSA 2009: 368-373
2007
[c28]
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  - conf/cf/MarquetDBMD07
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Philippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser:
Massively parallel processing on a chip. Conf. Computing Frontiers 2007: 277-286
[c27]
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Pierre Boulet, Philippe Marquet, Éric Piel, Julien Taillard:
Repetitive Allocation Modelling with MARTE. FDL 2007: 280-285
[c26]
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Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser:
A Design Flow to Map Parallel Applications onto FPGAs. FPL 2007: 605-608
[c25]
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Éric Piel, Philippe Marquet, Jean-Luc Dekeyser:
Model Transformations for the Compilation of Multi-processor Systems-on-Chip. GTTSE 2007: 459-473
[c24]
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Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser:
Multiple Abstraction Views of FPGA to Map Parallel Applications. ReCoSoC 2007: 90-97
[c23]
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Rabie Ben Atitallah, Éric Piel, Smaïl Niar, Philippe Marquet, Jean-Luc Dekeyser:
Multilevel MPSOC simulation using an MDE approach. SoCC 2007: 197-200
2006
[c22]
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  - conf/dsd/BeuxMLD06
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Sébastien Le Beux, Philippe Marquet, Ouassila Labbani, Jean-Luc Dekeyser:
FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar. DSD 2006: 280-287
[c21]
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Éric Piel, Philippe Marquet, Julien Soula, Jean-Luc Dekeyser:
Real-time systems for multiprocessor architectures. IPDPS 2006
2005
[c20]
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Samy Meftali, Anouar Dziri, Luc Charest, Philippe Marquet, J. Deskeyser:
SOAP Based Distributed Simulation Environment for SoC Design. FDL 2005: 283-291
[c19]
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Éric Piel, Philippe Marquet, Julien Soula, Jean-Luc Dekeyser:
Asymmetric Scheduling and Load Balancing for Real-Time on Linux SMP. PPAM 2005: 896-903
[c18]
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  - conf/uml/CuccuruDMB05
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Arnaud Cuccuru, Jean-Luc Dekeyser, Philippe Marquet, Pierre Boulet:
Towards UML 2 Extensions for Compact Modeling of Regular Complex Topologies. MoDELS 2005: 445-459
2004
[c17]
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Arnaud Cuccuru, Philippe Marquet, Jean-Luc Dekeyser:
UML2 as an ADL Hierarchichal Hardware Modeling. IFIP-WADL 2004: 133-147
[c16]
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Javed Dulloo, Philippe Marquet:
Design of a Real-Time Scheduler for Kahn Process Networks on Multiprocessor Systems. PDPTA 2004: 271-277
2003
[c15]
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Pierre Boulet, Jean-Luc Dekeyser, Cédric Dumoulin, Philippe Marquet:
MDA for SoC Design, Intensive Signal Processing Experiment. FDL 2003: 309-317
2002
[c14]
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  - conf/ipps/MomtchevM02
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Momtchil Momtchev, Philippe Marquet:
An Asymmetric Real-Time Scheduling for Linux. IPDPS 2002
[c13]
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  - conf/parelec/DevinBDM02
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Florent Devin, Pierre Boulet, Jean-Luc Dekeyser, Philippe Marquet:
GASPARD - A Visual Parallel Programming Environment. PARELEC 2002: 145-150
2001
[c12]
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Julien Soula, Philippe Marquet, Alain Demeure, Jean-Luc Dekeyser:
Compilation Principle of a Specification Language Dedicated to Signal Processing. PaCT 2001: 358-370
[c11]
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Pierre Boulet, Jean-Luc Dekeyser, Jean-Luc Levaire, Philippe Marquet, Julien Soula, Alain Demeure:
Visual Data-Parallel Programming for Signal Processing Applications. PDP 2001: 105-112

1990 – 1999

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1998
[j4]
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Cyril Fonlupt, Philippe Marquet, Jean-Luc Dekeyser:
Data-Parallel Load Balancing Strategies. Parallel Comput. 24(11): 1665-1684 (1998)
[c10]
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Dominique Sueur, Jean-Luc Dekeyser, Philippe Marquet:
DPFS: A Data-Parallel File System Environment. HPCN Europe 1998: 940-942
1996
[c9]
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  - conf/ac/DekeyserM96
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Jean-Luc Dekeyser, Philippe Marquet:
Supporting Irregular and Dynamic Computations in Data Parallel Languages. The Data Parallel Programming Model 1996: 197-219
[c8]
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  - conf/icip/GalinecDM96
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David Galinec, Jean-Luc Dekeyser, Philippe Marquet:
Mixed synchronous-asynchronous approach for real-time image processing: a MPEG-like coder. ICIP (2) 1996: 121-124
[c7]
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Jean-Luc Dekeyser, Boris Kokoszko, Jean-Luc Levaire, Philippe Marquet:
Irregular Data-Parallel Objects in C++. VECPAR 1996: 65-80
1995
[c6]
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Cyril Fonlupt, Philippe Marquet, Jean-Luc Dekeyser:
Analysis of Synchronous Dynamic Load Balancing Algorithms. PARCO 1995: 455-462
1994
[j3]
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Jean-Luc Dekeyser, Dominique Lazure, Philippe Marquet:
A Geometrical Data-Parallel Language. ACM SIGPLAN Notices 29(4): 31-40 (1994)
[c5]
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Cyril Fonlupt, Jean-Luc Dekeyser, Philippe Marquet:
Dynamic Load Balancing on SIMD Data-Parallel Computers. EUROSIM 1994: 219-226
[c4]
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Cyril Fonlupt, Philippe Marquet, Jean-Luc Dekeyser:
A Data-Parallel View of the Load Balancing - Experimental Results on MasPar MP-1. HPCN 1994: 338-343
1993
[c3]
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  - conf/hci/BenaliaDM93
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Akram-Djellal Benalia, Jean-Luc Dekeyser, Philippe Marquet:
HelpDraw Graphical Environment: A Step Beyond Data Parallel Programming Languages. HCI (2) 1993: 591-596
[c2]
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J.-L. Dekeyseer, Dominique Lazure, Philippe Marquet:
HELP for parallel scientific programming. PDP 1993: 22-29
1992
[c1]
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  - conf/isca/KechadiDMP92
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M. Tahar Kechadi, Jean-Luc Dekeyser, Philippe Marquet, Philippe Preux:
Performance improvement for vector pipeline multiprocessor systems using a disordered execution model. ISCA 1992: 433
1990
[j2]
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Jean-Luc Dekeyser, Philippe Marquet, Philippe Preux:
Vector addressing processor for direct and indirect accesses. Microprocessing and Microprogramming 30(1-5): 657-664 (1990)
[j1]
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Jean-Luc Dekeyser, Philippe Marquet, Philippe Preux:
EVA: an explicit vector language. ACM SIGPLAN Notices 25(8): 53-71 (1990)

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