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ORCIDSukarn Agarwal
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2020 – today
- 2024
[j7]Sangeet Saha
, Shounak Chakraborty, Sukarn Agarwal, Magnus Själander, Klaus D. McDonald-Maier:
ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 2944-2957 (2024)- [c17]Sukarn Agarwal, Shounak Chakraborty, Magnus Själander:
TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture. IPDPS 2024: 852-864 - 2023
- [j6]Andrés Goens, Soham Chakraborty, Susmit Sarkar, Sukarn Agarwal, Nicolai Oswald, Vijay Nagarajan:
Compound Memory Models. Proc. ACM Program. Lang. 7(PLDI): 1145-1168 (2023) - [j5]Sangeet Saha, Shounak Chakraborty, Sukarn Agarwal, Rahul Gangopadhyay, Magnus Själander, Klaus D. McDonald-Maier:
DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore. IEEE Trans. Parallel Distributed Syst. 34(2): 718-733 (2023) - [c16]Sukarn Agarwal, Shounak Chakraborty, Magnus Själander:
Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR). DAC 2023: 1-6 - 2021
- [j4]Sukarn Agarwal, Hemangee K. Kapoor:
Improving the Performance of Hybrid Caches Using Partitioned Victim Caching. ACM Trans. Embed. Comput. Syst. 20(1): 5:1-5:27 (2021) - [c15]Sukarn Agarwal, Shounak Chakraborty:
ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache. ASAP 2021: 171-174 - [c14]Mayank Baranwal, Udbhav Chugh, Shivang Dalal, Sukarn Agarwal, Hemangee K. Kapoor:
DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches. ISQED 2021: 469-475 - 2020
- [j3]Arijit Nath, Sukarn Agarwal, Hemangee K. Kapoor:
Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory System. ACM Trans. Design Autom. Electr. Syst. 25(3): 24:1-24:32 (2020) - [c13]Khushboo Rani, Sukarn Agarwal, Hemangee K. Kapoor:
DidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects. ISLPED 2020: 151-156 - [c12]Sukarn Agarwal, Hemangee K. Kapoor:
LiNoVo: Longevity Enhancement of Non-Volatile Last Level Caches in Chip Multiprocessors. ISVLSI 2020: 194-199
2010 – 2019
- 2019
- [j2]Sukarn Agarwal, Hemangee K. Kapoor:
Improving the Lifetime of Non-Volatile Cache by Write Restriction. IEEE Trans. Computers 68(9): 1297-1312 (2019) - [c11]Sukarn Agarwal, Hemangee K. Kapoor:
Enhancing the Lifetime of Non-Volatile Caches by Exploiting Module-Wise Write Restriction. ACM Great Lakes Symposium on VLSI 2019: 213-218 - [c10]Sheel Sindhu Manohar, Sukarn Agarwal, Hemangee K. Kapoor:
Towards Optimizing Refresh Energy in embedded-DRAM Caches using Private Blocks. ACM Great Lakes Symposium on VLSI 2019: 225-230 - 2018
- [j1]Sukarn Agarwal, Hemangee K. Kapoor:
Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1881-1894 (2018) - [c9]Khushboo Rani, Sukarn Agarwal, Hemangee K. Kapoor:
Non-blocking Gated Buffers for Energy Efficient on-chip Interconnects in the era of Dark Silicon. ISED 2018: 74-79 - [c8]Ashwini A. Kulkarni, Chirag Joshi, Khushboo Rani, Sukarn Agarwal, Shrinivas P. Mahajan, Hemangee K. Kapoor:
Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors. ISED 2018: 230-235 - [c7]Ashwini A. Kulkarni, Khushboo Rani, Sukarn Agarwal, Shrinivas P. Mahajan, Hemangee K. Kapoor:
Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors. iSES 2018: 52-57 - [c6]Sharma Priya, Sukarn Agarwal, Hemangee K. Kapoor:
Fault Tolerance in Network on Chip Using Bypass Path Establishing Packets. VLSID 2018: 457-458 - 2017
- [c5]Sukarn Agarwal, Hemangee K. Kapoor:
Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets. VLSI-SoC 2017: 1-6 - [c4]Sukarn Agarwal, Hemangee K. Kapoor:
Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management Techniques. VLSI-SoC (Selected Papers) 2017: 46-71 - [c3]Sukarn Agarwal, Hemangee K. Kapoor:
Towards a Better Lifetime for Non-volatile Caches in Chip Multiprocessors. VLSID 2017: 29-34 - 2016
- [c2]Sukarn Agarwal, Hemangee K. Kapoor:
Towards a dynamic associativity enabled write prediction based hybrid cache. VDAT 2016: 1-6 - [c1]Sukarn Agarwal, Hemangee K. Kapoor:
Restricting writes for energy-efficient hybrid cache in multi-core architectures. VLSI-SoC 2016: 1-6
Coauthor Index
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