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ORCIDSreeranga P. Rajan
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2020 – today
- 2022
[j10]Sankaran Narayanan, Kaivalya Mannam, Pradeep Achan, Maneesha V. Ramesh, P. Venkat Rangan, Sreeranga P. Rajan:
A contextual multi-task neural approach to medication and adverse events identification from clinical text. J. Biomed. Informatics 125: 103960 (2022)- 2021
- [j9]Sankaran Narayanan, Pradeep Achan, P. Venkat Rangan, Sreeranga P. Rajan:
Unified concept and assertion detection using contextual multi-task learning in a clinical decision support system. J. Biomed. Informatics 122: 103898 (2021) - 2020
- [c25]Sankaran Narayanan, Kaivalya Mannam, Sreeranga P. Rajan, P. Venkat Rangan:
Evaluation of Transfer Learning for Adverse Drug Event (ADE) and Medication Entity Extraction. ClinicalNLP@EMNLP 2020: 55-64
2010 – 2019
- 2018
- [c24]Sankaran Narayanan, Fensa Merry Saj, Kamal Bijlani, Sreeranga P. Rajan:
Automatic Assessment Item Bank Calibration for Learning Gap Identification. ICACCI 2018: 1429-1435 - 2017
- [j8]Hiroaki Yoshida, Guodong Li, Takuki Kamiya, Indradeep Ghosh
, Sreeranga P. Rajan, Susumu Tokumoto, Kazuki Munakata, Tadahiro Uehara:
KLOVER: Automatic Test Generation for C and C Programs, Using Symbolic Execution. IEEE Softw. 34(5): 30-37 (2017) - 2014
- [c23]Shiju Sathyadevan, Nandini Muraleedharan, Sreeranga P. Rajan:
Enhancement of Data Level Security in MongoDB. ISI (2) 2014: 199-212 - 2013
- [j7]Alvaro A. Cárdenas, Pratyusa K. Manadhata, Sreeranga P. Rajan:
Big Data Analytics for Security. IEEE Secur. Priv. 11(6): 74-76 (2013) - 2012
- [c22]Guodong Li, Peng Li, Geoffrey Sawaya, Ganesh Gopalakrishnan, Indradeep Ghosh, Sreeranga P. Rajan:
GKLEE: concolic verification and test generation for GPUs. PPoPP 2012: 215-224 - 2011
- [c21]Guodong Li, Indradeep Ghosh, Sreeranga P. Rajan:
KLOVER: A Symbolic Execution and Automatic Test Generation Tool for C++ Programs. CAV 2011: 609-615 - [c20]Oksana Tkachuk, Sreeranga P. Rajan:
Automated Driver Generation for Analysis of Web Applications. FASE 2011: 326-340 - [c19]Hideo Tanida, Masahiro Fujita, Mukul R. Prasad, Sreeranga P. Rajan:
Client-tier Validation of Dynamic Web Applications. ICSOFT (2) 2011: 86-95 - [c18]Hideo Tanida, Mukul R. Prasad, Sreeranga P. Rajan, Masahiro Fujita:
Automated System Testing of Dynamic Web Applications. ICSOFT (Selected Papers) 2011: 181-196
2000 – 2009
- 2009
- [c17]Sreeranga P. Rajan, Oksana Tkachuk, Mukul R. Prasad, Indradeep Ghosh, Nitin Goel, Tadahiro Uehara:
WEAVE: WEb Applications Validation Environment. ICSE Companion 2009: 101-111 - 2008
- [c16]Xin Li, Daryl Shannon, Indradeep Ghosh, Mizuhito Ogawa, Sreeranga P. Rajan, Sarfraz Khurshid:
Context-Sensitive Relevancy Analysis for Efficient Symbolic Execution. APLAS 2008: 36-52 - 2007
- [c15]Oksana Tkachuk, Sreeranga P. Rajan:
Combining environment generation and slicing for modular software model checking. ASE 2007: 401-404 - 2006
- [j6]David W. Currie, Xiushan Feng, Masahiro Fujita, Alan J. Hu, Mark Kwan, Sreeranga P. Rajan:
Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions. Int. J. Parallel Program. 34(1): 61-91 (2006) - [c14]Oksana Tkachuk, Sreeranga P. Rajan:
Application of automated environment generation to commercial software. ISSTA 2006: 203-214 - 2005
- [j5]Sreeranga P. Rajan:
Editorial. ACM Trans. Storage 1(1): 1-2 (2005) - [c13]Graham Hughes, Sreeranga P. Rajan, Tom Sidle, Keith D. Swenson:
Error Detection in Concurrent Java Programs. SoftMC@CAV 2005: 45-58 - 2004
- [c12]Praveen K. Murthy, Sreeranga P. Rajan, Koichiro Takayama:
High level hardware validation using hierarchical message sequence charts. HLDVT 2004: 167-172 - 2002
- [j4]Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum:
Program slicing for VHDL. Int. J. Softw. Tools Technol. Transf. 4(1): 125-137 (2002) - [c11]Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan:
Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract). ASP-DAC/VLSI Design 2002: 11-13 - 2001
- [j3]Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama:
A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(11): 1319-1328 (2001) - 2000
- [c10]David W. Currie, Alan J. Hu, Sreeranga P. Rajan:
Automatic formal verification of DSP software. DAC 2000: 130-135
1990 – 1999
- 1999
- [c9]Vamsi Boppana, Sreeranga P. Rajan, Koichiro Takayama, Masahiro Fujita:
Model Checking Based on Sequential ATPG. CAV 1999: 418-430 - [c8]Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum:
Program Slicing of Hardware Description Languages. CHARME 1999: 298-312 - [c7]Sreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsanam, Sharad Malik:
Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor. CODES 1999: 2-6 - 1998
- [j2]Sreeranga P. Rajan, Masahiro Fujita, K. Yuan, Mike Tien-Chien Lee:
ATM switch design by high-level modeling, formal verification and high-level synthesis. ACM Trans. Design Autom. Electr. Syst. 3(4): 554-562 (1998) - [c6]Masahiro Fujita, Sreeranga P. Rajan, Alan J. Hu:
Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol. FM-Trends 1998: 281-295 - [c5]Sreeranga P. Rajan, Masahiro Fujita:
Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design. VLSI Design 1998: 552-557 - 1997
- [c4]Sreeranga P. Rajan, Masahiro Fujita:
ATM Switch Design: Parametric High-Level Modeling and Formal Verification. AMAST 1997: 437-450 - [c3]Sreeranga P. Rajan, Natarajan Shankar, Mandayam K. Srivas:
Industrial Strength Formal Verification Techniques for Hardware Designs. VLSI Design 1997: 208-212 - 1996
- [j1]Peter F. A. Middelhoek, Sreeranga P. Rajan:
From VHDL to efficient and first-time-right designs: a formal approach. ACM Trans. Design Autom. Electr. Syst. 1(2): 205-250 (1996) - 1993
- [c2]Sreeranga P. Rajan, Jeffrey J. Joyce, Carl-Johan H. Seger:
From Abstract Data Types to Shift Registers: A Case Study in Formal Specification and Verification at Differing Levels of Abstraction using Theorem Proving and Symbolic Simulation. HUG 1993: 489-500 - 1992
- [c1]Sreeranga P. Rajan:
Executing HOL Specifications: Towards an Evaluation Semantics for Classical Higher Order Logic. TPHOLs 1992: 527-536
Coauthor Index
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