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ORCIDWilliam Andrew Simon
Person information
- affiliation: École Polytechnique Fédérale de Lausanne, Vaud, Switzerland
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2020 – today
- 2022
[c15]William Andrew Simon, Una Pale, Tomás Teijeiro
, David Atienza:
HDTorch: Accelerating Hyperdimensional Computing with GP-GPUs for Design Space Exploration. ICCAD 2022: 83:1-83:8- [i1]William Andrew Simon, Una Pale, Tomás Teijeiro, David Atienza:
HDTorch: Accelerating Hyperdimensional Computing with GP-GPUs for Design Space Exploration. CoRR abs/2206.04746 (2022) - 2021
- [j2]Yasir Mahmood Qureshi, William Andrew Simon, Marina Zapater, Katzalin Olcoz, David Atienza:
Gem5-X: A Many-core Heterogeneous Simulation Platform for Architectural Exploration and Optimization. ACM Trans. Archit. Code Optim. 18(4): 44:1-44:27 (2021) - [c14]William Andrew Simon, Valérian Ray, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, David Atienza:
Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding. DAC 2021: 805-810 - 2020
- [j1]William Andrew Simon, Yasir Mahmood Qureshi, Marco Rios, Alexandre Levisse, Marina Zapater, David Atienza:
BLADE: An in-Cache Computing Architecture for Edge Devices. IEEE Trans. Computers 69(9): 1349-1363 (2020) - [c13]William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza:
A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance. VLSI-SOC 2020: 94-99
2010 – 2019
- 2019
- [c12]William Andrew Simon, Juan Galicia, Alexandre Levisse, Marina Zapater, David Atienza:
A Fast, Reliable and Wide-Voltage-Range In-Memory Computing Architecture. DAC 2019: 83 - [c11]William Andrew Simon, Yasir Mahmood Qureshi, Alexandre Levisse, Marina Zapater, David Atienza:
BLADE: A BitLine Accelerator for Devices on the Edge. ACM Great Lakes Symposium on VLSI 2019: 207-212 - [c10]Alexandre Levisse, Marco Rios, William Andrew Simon, Pierre-Emmanuel Gaillardon, David Atienza:
Functionality Enhanced Memories for Edge-AI Embedded Systems. NVMTS 2019: 1-4 - [c9]Yasir Mahmood Qureshi, William Andrew Simon, Marina Zapater, David Atienza, Katzalin Olcoz:
Gem5-X: A Gem5-Based System Level Simulation Framework to Optimize Many-Core Platforms. SpringSim 2019: 1-12 - [c8]Marco Rios, William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza:
An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication. VLSI-SoC 2019: 34-39 - 2018
- [c7]Arman Iranfar, William Andrew Simon, Marina Zapater, David Atienza:
A Machine Learning-Based Strategy for Efficient Resource Management of Video Encoding on Heterogeneous MPSoCs. ISCAS 2018: 1-5 - 2017
- [c6]Aya Ibrahim, William Andrew Simon, Damien Doy, Eliéva Pignat, Federico Angiolini, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli:
Single-FPGA complete 3D and 2D medical ultrasound imager. DASIP 2017: 1-6 - [c5]Federico Angiolini, Aya Ibrahim, William Andrew Simon, Ahmet Caner Yuzuguler, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli:
1024-Channel 3D ultrasound digital beamformer in a single 5W FPGA. DATE 2017: 1225-1228 - [c4]Arman Iranfar, Federico Terraneo, William Andrew Simon, Leon Dragic, Igor Piljic, Marina Zapater, William Fornaciari, Mario Kovac, David Atienza:
Thermal characterization of next-generation workloads on heterogeneous MPSoCs. SAMOS 2017: 286-291 - 2016
- [c3]Ahmet Caner Yuzuguler, William Andrew Simon, Aya Ibrahim, Federico Angiolini, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli:
Demo: Efficient delay and apodization for on-FPGA 3D ultrasound. DASIP 2016: 227-228 - [c2]William Andrew Simon, Ahmet Caner Yuzuguler, Aya Ibrahim, Federico Angiolini, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli:
Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer. FPL 2016: 1-2 - [c1]Ahmet Caner Yuzuguler, William Andrew Simon, Aya Ibrahim, Federico Angiolini, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli:
Single-FPGA 3D ultrasound beamformer. FPL 2016: 1
Coauthor Index
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