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ORCIDMahendra Sakare
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2020 – today
- 2024
[j5]Sahibia Kaur Vohra
, Sherin A. Thomas, Mahendra Sakare, Devarshi Mrinal Das:
Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons. Integr. 95: 102122 (2024)- 2023
- [j4]Mayank Kumar Singh, Puneet Singh, Upendra Chichhula, Hirensh Mehra, Devarshi Mrinal Das, Mahendra Sakare:
A PRBS Generator Using Merged XOR-D Flip-Flop as Building Blocks. Circuits Syst. Signal Process. 42(11): 6813-6828 (2023) - [j3]Sahibia Kaur Vohra, Sherin A. Thomas, Shivdeep, Mahendra Sakare, Devarshi Mrinal Das:
Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse. IEEE Trans. Very Large Scale Integr. Syst. 31(7): 993-1003 (2023) - [c12]Mayank Kumar Singh, Manish Kumar Gautam, Puneet Singh, R. Nagulapalli, Devarshi Mrinal Das, Mahendra Sakare:
A Double Cross-Coupled Delay Cell for High-Frequency Differential Ring VCOs. APCCAS 2023: 1-5 - [c11]Sahibia Kaur Vohra, Alex Pappachen James, Mahendra Sakare, Devarshi Mrinal Das:
Analysing Mismatch effect of CMOS Neurons in Spiking Neural Network with Winner-take-all Mechanism. NorCAS 2023: 1-7 - [c10]Mayank Kumar Singh, Puneet Singh, Devarshi Mrinal Das, Mahendra Sakare:
A Low Power Differential Delay Cell without Cross-Coupled Latch for Ring VCO. PRIME 2023: 145-148 - 2022
- [i1]Sahibia Kaur Vohra, Sherin A. Thomas, Mahendra Sakare, Devarshi Mrinal Das:
CMOS Circuit Implementation of Spiking Neural Network for Pattern Recognition Using On-chip Unsupervised STDP Learning. CoRR abs/2204.04430 (2022) - 2021
- [c9]Sahibia Kaur Vohra, Sherin A. Thomas, Mahendra Sakare, Devarshi Mrinal Das:
Full CMOS Implementation of Bidirectional Associative Memory Neural Network with Analog Memristive Synapse. MWSCAS 2021: 445-448 - [c8]Mayank Kumar Singh, Puneet Singh, Devarshi Mrinal Das, Mahendra Sakare:
A low power 8 × 27-1 PRBS generator using Exclusive-OR gate merged D flip-flops. MWSCAS 2021: 779-782 - [c7]Puneet Singh, Mayank Kumar Singh, Vinayak Gopal Hande, Mahendra Sakare:
Design of a PRBS generator and a serializer using active inductor employed CML latch. MWSCAS 2021: 802-805 - [c6]Sahibia Kaur Vohra, Sherin A. Thomas, Mahendra Sakare, Devarshi Mrinal Das:
Analytical Modelling of a CMOS Inter Spike Interval Decoder for Resistive Crossbar based Brain Inspired Computing. VDAT 2021: 1-4
2010 – 2019
- 2017
- [j2]Mahendra Sakare:
A Power and Area Efficient Architecture of a PRBS Generator With Multiple Outputs. IEEE Trans. Circuits Syst. II Express Briefs 64-II(8): 927-931 (2017) - 2016
- [j1]Mahendra Sakare, Sadhu Pavan Kumar, Shalabh Gupta:
Bandwidth Enhancement of Flip-Flops Using Feedback for High-Speed Integrated Circuits. IEEE Trans. Circuits Syst. II Express Briefs 63-II(8): 768-772 (2016) - [c5]Mahendra Sakare:
A Quarter-Rate 27-1 Pseudo-Random Binary Sequence Generator Using Interleaved Architecture. VLSID 2016: 196-201 - [c4]Pragya Maheshwari, Suhas Kaushik, Mahendra Sakare, Shalabh Gupta:
A 12.5 Gbps One-Fifth Rate CDR Incorporating a Novel Sampler Based Phase Detector and a DFE. VLSID 2016: 555-556 - 2014
- [c3]Mahendra Sakare, Shalabh Gupta:
A high-speed PRBS generator using flip-flops employing feedback for distributed equalization. ISCAS 2014: 746-749 - 2012
- [c2]Mahendra Sakare, Mohit Singh, Shalabh Gupta:
A 4 × 20 Gb/s 29-1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology. VDAT 2012: 252-257 - 2011
- [c1]Mohit Singh, Mahendra Sakare, Shalabh Gupta:
Testing of high-speed DACs using PRBS generation with "Alternate-Bit-Tapping". DATE 2011: 377-382
Coauthor Index
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