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2020 – today
- 2020
[c19]Rodrigo C. O. Rocha, Vasileios Porpodas, Pavlos Petoumenos, Luís F. W. Góes
, Zheng Wang, Murray Cole, Hugh Leather:
Vectorization-aware loop unrolling with seed forwarding. CC 2020: 1-13
2010 – 2019
- 2019
- [c18]Vasileios Porpodas, Rodrigo C. O. Rocha, Evgueni Brevnov, Luís F. W. Góes, Timothy G. Mattson:
Super-Node SLP: Optimized Vectorization for Code Sequences Containing Operators and Their Inverse Elements. CGO 2019: 206-216 - [c17]Vasileios Porpodas, Pushkar Ratnalikar:
PostSLP: Cross-Region Vectorization of Fully or Partially Vectorized Code. LCPC 2019: 15-31 - [i1]Vasileios Porpodas:
ZOFI: Zero-Overhead Fault Injection Tool for Fast Transient Fault Coverage Analysis. CoRR abs/1906.09390 (2019) - 2018
- [c16]Vasileios Porpodas, Rodrigo C. O. Rocha, Luís F. W. Góes:
VW-SLP: auto-vectorization with adaptive vector width. PACT 2018: 12:1-12:15 - [c15]Vasileios Porpodas, Rodrigo C. O. Rocha, Luís F. W. Góes:
Look-ahead SLP: auto-vectorization in the presence of commutative operations. CGO 2018: 163-174 - 2017
- [c14]Vasileios Porpodas:
SuperGraph-SLP Auto-Vectorization. PACT 2017: 330-342 - [c13]Xinmin Tian, Hideki Saito, Ernesto Su, Jin Lin, Satish Guggilla, Diego Caballero, Matt Masten, Andrew Savonichev, Michael Rice, Elena Demikhovsky, Ayal Zaks, Gil Rapaport, Abhinav Gaba, Vasileios Porpodas, Eric N. Garcia:
LLVM Compiler Implementation for Explicit Parallelization and SIMD Vectorization. LLVM-HPC@SC 2017: 4:1-4:11 - 2016
- [c12]Konstantina Mitropoulou, Vasileios Porpodas, Timothy M. Jones:
COMET: communication-optimised multi-threaded error-detection technique. CASES 2016: 7:1-7:10 - [c11]Konstantina Mitropoulou, Vasileios Porpodas, Xiaochun Zhang, Timothy M. Jones:
Lynx: Using OS and Hardware Support for Fast Fine-Grained Inter-Core Communication. ICS 2016: 18:1-18:12 - 2015
- [c10]Vasileios Porpodas, Timothy M. Jones:
Throttling Automatic Vectorization: When Less is More. PACT 2015: 432-444 - [c9]Vasileios Porpodas, Alberto Magni, Timothy M. Jones:
PSLP: padded SLP automatic vectorization. CGO 2015: 190-201 - 2013
- [c8]Vasileios Porpodas, Marcelo Cintra:
CAeSaR: Unified cluster-assignment scheduling and communication reuse for clustered VLIW processors. CASES 2013: 9:1-9:10 - [c7]Konstantina Mitropoulou, Vasileios Porpodas, Marcelo Cintra:
CASTED: Core-Adaptive Software Transient Error Detection for Tightly Coupled Cores. IPDPS 2013: 513-524 - [c6]Konstantina Mitropoulou, Vasileios Porpodas, Marcelo Cintra:
DRIFT: Decoupled CompileR-Based Instruction-Level Fault-Tolerance. LCPC 2013: 217-233 - [c5]Vasileios Porpodas, Marcelo Cintra:
Aligned Scheduling: Cache-Efficient Instruction Scheduling for VLIW Processors. LCPC 2013: 275-291 - [c4]Vasileios Porpodas, Marcelo Cintra:
LUCAS: latency-adaptive unified cluster assignment and instruction scheduling. LCTES 2013: 45-54 - 2012
- [c3]Karthik T. Sundararajan, Vasileios Porpodas, Timothy M. Jones, Nigel P. Topham, Björn Franke:
Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPs. HPCA 2012: 311-322 - [c2]Vasileios Porpodas, Marcelo Cintra:
UCIFF: Unified Cluster Assignment Instruction Scheduling and Fast Frequency Selection for Heterogeneous Clustered VLIW Cores. LCPC 2012: 127-142 - 2010
- [j2]Athanasios Milidonis, Nikolaos Alachiotis, Vasileios Porpodas, Harris E. Michail, George A. Panagiotakopoulos, Athanasios P. Kakarountas, Costas E. Goutis:
Decoupled Processors Architecture for Accelerating Data Intensive Applications using Scratch-Pad Memory Hierarchy. J. Signal Process. Syst. 59(3): 281-296 (2010)
2000 – 2009
- 2009
- [j1]Athanasios Milidonis, Vasileios Porpodas, Nikolaos Alachiotis, Athanasios P. Kakarountas, Harris E. Michail, George A. Panagiotakopoulos, Costas E. Goutis:
Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse. IET Comput. Digit. Tech. 3(1): 109-123 (2009) - 2007
- [c1]Athanasios Milidonis, Nikolaos Alachiotis, Vasileios Porpodas, Haralambos Michail, Athanasios Kakarountas, Constantinos E. Goutis:
Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy. DATE 2007: 612-617
Coauthor Index
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