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2020 – today
- 2024
[c8]Nesara Eranna Bethur, Pruek Vanna-Iampikul, Odysseas Zografos, Lingjun Zhu, Giuliano Sisto, Dragomir Milojevic, Alberto García Ortiz, Geert Hellings, Julien Ryckaert, Francky Catthoor, Sung Kyu Lim:
GNN-assisted Back-side Clock Routing Methodology for Advance Technologies. DAC 2024: 287:1-287:6- [c7]Yun Zhou, S. C. Song, Halil Kükner, Giuliano Sisto, Sheng Yang, Anita Farokhnejad, Mohamed Naeim, Moritz Brunion, Ji-Yung Lin, Odysseas Zografos, Pieter Weckx, Shashank Ekbote, Nick Stevens-Yu, David Greenlaw, Steve Molloy, Geert Hellings, Julien Ryckaert:
Backside Power Delivery in High Density and High Performance Context: IR-Drop and Block-Level Power-Performance-Area Benefits. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c6]Mohamed Naeim
, Hanqi Yang, Pinhong Chen, Rong Bao, Antoine Dekeyser, Giuliano Sisto, Moritz Brunion, Rongmei Chen, Geert Van der Plas, Eric Beyne, Dragomir Milojevic:
Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs. 3DIC 2023: 1-4 - [c5]Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Yun Zhou, Ivan Ciofi, Anne Jourdain, A. Veloso, Michele Stucchi, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert:
Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j1]Giuliano Sisto, Odysseas Zografos, Bilal Chehab, Naveen Kakarla, Yang Xiang, Dragomir Milojevic, Pieter Weckx, Geert Hellings, Julien Ryckaert:
Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1497-1506 (2022) - [c4]Rongmei Chen, Giuliano Sisto, Odysseas Zografos, Dragomir Milojevic, Pieter Weckx, Geert Van der Plas, Eric Beyne:
Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper. SLIP 2022: 3:1-3:5 - [c3]Rongmei Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, Anabela Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne:
Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. VLSI Technology and Circuits 2022: 429-430 - 2021
- [c2]Giuliano Sisto, Rongmei Chen, Richard Chou, Geert Van der Plas, Eric Beyne, Rod Metcalfe, Dragomir Milojevic:
Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited). SLIP 2021: 17-23
2010 – 2019
- 2019
- [c1]Giuliano Sisto, Peter Debacker, Rongmei Chen, Geert Van der Plas, Richard Chou, Eric Beyne, Dragomir Milojevic:
Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route. 3DIC 2019: 1-4
Coauthor Index
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