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2020 – today
- 2024
[c7]Daewon Ha, Y. Lee, S. Yoo, W. Lee, M. H. Cho, K. Yoo, S. M. Lee, S. Lee, M. Terai, T. H. Lee, J. H. Bae, K. J. Moon, C. Sung, M. Hong, D. G. Cho, K. Lee, S. W. Park, K. Park, Bong Jin Kuh, S. Hyun, Sujin Ahn, J. H. Song:
Exploring Innovative IGZO-channel based DRAM Cell Architectures and Key Technologies for Sub-10nm Node. IMW 2024: 1-4- [c6]Taeyoung Kim, Suhwan Lim, Ilho Myeong, Sanghyun Park, Suseong Noh, Seung Min Lee, Jongho Woo, Hanseung Ko, Youngji Noh, Moonkang Choi, Kiheun Lee, Sangwoo Han, Jongyeon Baek, Kijoon Kim, Dongjin Jung, Jisung Kim, Jaewoo Park, Seunghyun Kim, Hyoseok Kim, Sijung Yoo, Hyun Jae Lee, Duk-Hyun Choe, Seung-Geol Nam, Ilyoung Yoon, Chaeho Kim, Kwanzsoo Kim, Kwanzmin Park, Bong Jin Kuh, Jinseong Heo, Wanki Kim, Daewon Ha, Jaihyuk Song:
Drain Current Degradation Induced by Charge Trapping/De-Trapping in Fe-FET. IRPS 2024: 6 - [c5]Ilho Myeong, Suhwan Lim, Taeyoung Kim, Sanghyun Park, Suseong Noh, Seung Min Lee, Jongho Woo, Hanseung Ko, Youngji Noh, Munkang Choi, Kiheun Lee, Sangwoo Han, Jongyeon Baek, Kijoon Kim, Dongjin Jung, Jisung Kim, Jaewoo Park, Seunghyun Kim, Hyoseok Kim, Ilyounz Yoon, Jaeho Kim, Kwangsoo Kim, Kwangmin Park, Bong Jin Kuh, Wanki Kim, Daewon Ha, Sujin Ahn, Jaihyuk Song, Sijung Yoo, Hyun Jae Lee, Duk-Hyun Choe, Seung-Geol Nam, Jinseong Heo:
A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND. IRPS 2024: 9 - [c4]Jaehyun Park, Juhun Park, Kyuman Hwang, Jinchan Yun, Dahye Kim, Sungil Park, Jejune Park, Jinwook Yang, Jae Won Jeong, Chuljin Yun, Jinho Bae, Sam Park, Daihong Huh, Sanghyeon Kim, Seungeun Baek, Suk Yang, Inhae Zoh, Junghan Lee, Tae-sun Kim, Younsu Ha, Sun-Jung Lee, Sang Wuk Park, Bong Jin Kuh, Daewon Ha, Sangjin Hyun, Sujin Ahn, Jaihyuk Song:
Highly manufacturable Self-Aigned Direct Backside Contact (SA-DBC) and Backside Gate Contact (BGC) for 3-dimensional Stacked FET at 48nm gate pitch. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c3]Jung-Won Han, S. H. Park, Moonyoung Jeong, K. N. Kim, H. J. Kim, J. C. Shin, S. M. Park, S. H. Shin, S. W. Park, K. S. Lee, J. H. Lee, S. H. Kim, B. C. Kim, Myoung H. Jung, I. Y. Yoon, H. Kim, S. U. Jang, K. J. Park, Y. K. Kim, I. G. Kim, J. H. Oh, S. Y. Han, B. S. Kim, Bong Jin Kuh, J. M. Park:
Ongoing Evolution of DRAM Scaling via Third Dimension -Vertically Stacked DRAM -. VLSI Technology and Circuits 2023: 1-2
2010 – 2019
- 2014
- [c2]Ho-Chul Ji, Kwansik Cho, Beomsuk Lee, K. Y. Cho, S. H. Choi, J. H. Kim, Yonghwack Shin, S. G. Kim, S. Y. Lee, Hyunil Byun, S. Parmar, A. H. Nejadmalayeri, D. H. Kim, J. K. Bok, Y. S. Park, Dongjae Shin, I. S. Joe, Bong Jin Kuh, B. S. Kim, K. C. Kim, H. M. Choi, Kyoungho Ha:
BOX-less waveguide Ge PD for bulk-Si based silicon photonic platform. OFC 2014: 1-3 - 2013
- [c1]Dongjae Shin, Kwansik Cho, Ho-Chul Ji, Beomsuk Lee, S. G. Kim, J. K. Bok, S. H. Choi, Yonghwack Shin, J. H. Kim, S. Y. Lee, K. Y. Cho, Bong Jin Kuh, J. H. Shin, J. S. Lim, J. M. Kim, H. M. Choi, Kyoungho Ha, Y. D. Park, C. H. Chung:
Integration of silicon photonics into DRAM process. OFC/NFOEC 2013: 1-3
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