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ORCIDFelipe S. Marques 0001
Person information
- affiliation: University of Pelotas, Technology Development Center, Brazil
- affiliation: Federal University of Pelotas, Group ofArchitectures and Integrated Circuits, GACI, Brazil
- affiliation: Nangate Inc
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2020 – today
- 2022
[j6]Julio Saraçol Domingues Júnior
, Leomar Soares da Rosa Jr., Felipe de Souza Marques:
Migortho: A Design Automation Flow for QCA Circuits. IEEE Des. Test 39(2): 23-30 (2022)- 2021
- [j5]Stephano Machado Moreira Goncalves, Leomar S. da Rosa Jr., Felipe S. Marques:
SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling. ACM Trans. Design Autom. Electr. Syst. 26(2): 9:1-9:38 (2021) - 2020
- [j4]Stéphano M. M. Gonçalves, Leomar S. da Rosa Jr., Felipe de Souza Marques:
DRAPS: A Design Rule Aware Path Search Algorithm for Detailed Routing. IEEE Trans. Circuits Syst. II Express Briefs 67-II(7): 1239-1243 (2020) - [c34]Maicon Schneider Cardoso, Andrei A. O. Bubolz, Jordi Cortadella, Leomar Rosa, Felipe S. Marques:
Transistor Placement for Automatic Cell Synthesis through Boolean Satisfiability. ISCAS 2020: 1-5 - [c33]Julio Saraçol Domingues Júnior, Leomar Soares da Rosa Jr., Felipe de Souza Marques:
A Straightforward Methodology for QCA Circuits Design. SBCCI 2020: 1-6
2010 – 2019
- 2019
- [c32]Stéphano M. M. Gonçalves, Leomar S. da Rosa, Felipe S. de Marques:
An Improved Heuristic Function for A∗-Based Path Search in Detailed Routing. ISCAS 2019: 1-5 - [c31]Vitor G. Lima, Guilherme Paim, Leandro M. G. Rocha, Leomar S. da Rosa Jr., Felipe S. Marques, Eduardo A. C. da Costa, Vinicius V. Camargo, Rafael Soares, Sergio Bampi:
Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing. ISCAS 2019: 1-5 - 2018
- [j3]Maicon Schneider Cardoso, Gustavo H. Smaniotto, Andrei A. O. Bubolz, Matheus T. Moreira, Leomar S. da Rosa Jr., Felipe de Souza Marques:
Libra: An Automatic Design Methodology for CMOS Complex Gates. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1345-1349 (2018) - [c30]Vitor G. Lima, Plinio Finkenauer, Vinicius V. Camargo, Felipe S. Marques, Leomar R. Junior, Rafael Iankowski Soares:
A Novel Sizing Method Aiming Security Against Differential Power Analysis. ICECS 2018: 429-432 - [c29]Stéphano M. M. Gonçalves, Leomar S. da Rosa, Felipe S. de Marques:
A New Technique Using Tunnel Shape Information to Improve Path Search in Detailed Routing. NEWCAS 2018: 243-247 - [c28]Maicon Schneider Cardoso, Gustavo H. Smaniotto, Andrei A. O. Bubolz, Leomar S. da Rosa Jr., Felipe S. Marques:
Area-Aware Design of Static CMOS Complex Gates. NEWCAS 2018: 282-286 - 2017
- [j2]Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.:
Transistor Count Optimization in IG FinFET Network Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(9): 1483-1496 (2017) - [c27]Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.:
A post-processing methodology to improve the automatic design of CMOS gates at layout-level. ICECS 2017: 42-45 - [c26]Stephano Machado Moreira Goncalves, Leomar S. da Rosa Jr., Felipe de Souza Marques:
A survey of path search algorithms for VLSI detailed routing. ISCAS 2017: 1-4 - [c25]Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.:
Post-processing of supergate networks aiming cell layout optimization. ISCAS 2017: 1-4 - [c24]Matheus Nachtigall, Paulo Ferreira, Felipe S. Marques:
Simulated Annealing Applied to LUT-Based FPGA Technology Mapping. MICAI (Special Session) 2017: 23-29 - [c23]Maicon Schneider Cardoso, Gustavo H. Smaniotto, Joao Junior da Silva Machado, Matheus T. Moreira, Leomar S. da Rosa, Felipe de Souza Marques:
Transistor placement strategies for non-series-parallel cells. MWSCAS 2017: 523-526 - 2016
- [j1]Vinicius Neves Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.:
Graph-Based Transistor Network Generation Method for Supergate Design. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 692-705 (2016) - [c22]Maicon Schneider Cardoso, Regis Zanandrea, Renato Souza de Souza, Joao Junior da Silva Machado, Leomar Soares da Rosa Jr., Felipe de Souza Marques:
Topological characteristics of logic networks generated by a graph-based methodology. LASCAS 2016: 343-346 - [c21]Gustavo H. Smaniotto, Joao Junior da Silva Machado, Matheus T. Moreira, Adriel Mota Ziesemer, Felipe S. Marques, Leomar S. da Rosa Jr.:
Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool. LASCAS 2016: 355-358 - [c20]Maicon Schneider Cardoso, Gustavo H. Smaniotto, Regis Zanandrea, Renato Souza de Souza, Leomar S. da Rosa, Felipe de Souza Marques:
Physical design of supergate cells aiming geometrical optimizations. MWSCAS 2016: 1-4 - [c19]Gustavo H. Smaniotto, Matheus T. Moreira, Adriel Mota Ziesemer, Felipe S. Marques, Leomar S. da Rosa:
Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding. MWSCAS 2016: 1-4 - 2015
- [c18]Maicon Schneider Cardoso, Leomar Soares da Rosa Jr., Felipe de Souza Marques:
Evaluating Geometric Aspects of Non-Series-Parallel Cells. SBCCI 2015: 16:1-16:6 - 2014
- [c17]Stephano Machado Moreira Goncalves, Leomar Soares da Rosa Jr., Felipe de Souza Marques:
A new general purpose line probe routing algorithm. ICECS 2014: 658-661 - [c16]Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar Soares da Rosa Jr.:
Exploring Independent Gates in FinFET-Based Transistor Network Generation. SBCCI 2014: 41:1-41:6 - 2013
- [c15]Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.:
Efficient transistor-level design of CMOS gates. ACM Great Lakes Symposium on VLSI 2013: 191-196 - [c14]Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
Transistor-level optimization of CMOS complex gates. LASCAS 2013: 1-4 - [c13]Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.:
Improving the methodology to build non-series-parallel transistor arrangements. SBCCI 2013: 1-6 - 2012
- [c12]Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements. SBCCI 2012: 1-6 - [c11]Andrws Vieira, Daniel Debastiani, Luciano Volcan Agostini, Felipe S. Marques, Júlio C. B. de Mattos:
Performance and Energy Consumption Analysis of Embedded Applications Based on Android Platform. SBESC 2012: 59-64 - 2010
- [c10]Osvaldo Martinello, Felipe S. Marques, Renato P. Ribas, André Inácio Reis:
KL-Cuts: A new approach for logic synthesis targeting multiple output blocks. DATE 2010: 777-782 - [c9]Vinicius Callegaro, Felipe de Souza Marques, Carlos Eduardo Klock, Leomar Soares da Rosa Jr., Renato P. Ribas, André Inácio Reis:
SwitchCraft: a framework for transistor network design. SBCCI 2010: 49-53 - [c8]Felipe S. Marques, Osvaldo Martinello, Renato P. Ribas, André Inácio Reis:
Improvements on the detection of false paths by using unateness and satisfiability. SBCCI 2010: 192-197
2000 – 2009
- 2008
- [c7]Tiago Muller Gil Cardoso, Leomar S. da Rosa Jr., Felipe de Souza Marques, Renato P. Ribas, André Inácio Reis:
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering. ISQED 2008: 47-52 - 2007
- [c6]Felipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis:
DAG based library-free technology mapping. ACM Great Lakes Symposium on VLSI 2007: 293-298 - [c5]Leomar S. da Rosa Jr., André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Felipe Ribeiro Schneider:
A comparative study of CMOS gates with minimum transistor stacks. SBCCI 2007: 93-98 - 2006
- [c4]Leomar S. da Rosa Jr., Felipe S. Marques, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis:
Fast disjoint transistor networks from BDDs. SBCCI 2006: 137-142 - 2005
- [c3]Felipe S. Marques, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis:
A new approach to the use of satisfiability in false path detection. ACM Great Lakes Symposium on VLSI 2005: 308-311 - 2002
- [c2]Felipe S. Marques, Vinícius P. Correia, A. Prado, Marcelo Lubaszewski, André Inácio Reis:
Testability Properties of BDDs. SBCCI 2002: 83-88 - [c1]Renato Fernandes Hentschke, Felipe S. Marques, Fernanda Lima, Luigi Carro, Altamiro Amadeu Susin, Ricardo Reis:
Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy. SBCCI 2002: 95-100
Coauthor Index
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