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Dharmaray Nedalgi

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2020 – today

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2024
[j3]
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Dharmaray Nedalgi, Saroja V. Siddamal, S. S. Kerur:
2×VDD IO buffer with 1×VDD devices considering hot-carrier and gate-oxide reliability issues. Integr. 98: 102230 (2024)
2023
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Dharmaray Nedalgi, Lavanya M. N, Saroja V. Siddamal:
Supply Noise and Peak Current Reduction in High-Speed Output Drivers. VLSID 2023: 127-132
2022
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Dharmaray Nedalgi, Saroja V. Siddamal:
Differential receiver with 2 × VDD input signals using 1 × VDD devices. Integr. 87: 306-312 (2022)
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Dharmaray Nedalgi, Saroja V. Siddamal:
Mixed-Voltage I/O Buffer Using NMOS Blocking Considering Gate Oxide Reliability. J. Circuits Syst. Comput. 31(11): 2250202:1-2250202:13 (2022)
2021
[c3]
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Dharmaray Nedalgi, Saroja V. Siddamal:
Novel Gate Tracking and N-well Control Circuit for $2\times \text{VDD}$ Tolerant I/O Buffer. APCCAS 2021: 93-96
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Dharmaray Nedalgi, Saroja V. Siddamal:
$2 \times \text{VDD}$ Tolerant I/O with Considerations of Hot-Carrier Degradation and Gate-Oxide Reliability. APCCAS 2021: 97-100
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Dharmaray Nedalgi, Saroja V. Siddamal:
High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zone. VLSID 2021: 135-138

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