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ORCIDMatteo Perotti
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2020 – today
- 2024
[j2]Matteo Perotti
, Matheus A. Cavalcante, Renzo Andri, Lukas Cavigelli, Luca Benini:
Ara2: Exploring Single- and Multi-Core Vector Processing With an Efficient RVV 1.0 Compliant Open-Source Processor. IEEE Trans. Computers 73(7): 1822-1836 (2024)- [c10]Matteo Perotti, Michele Raeber, Mattia Sinigaglia, Matheus A. Cavalcante, Davide Rossi, Luca Benini:
Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads. ASAP 2024: 172-173 - [c9]Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini:
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication. DATE 2024: 1-6 - [c8]Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini:
Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV. DATE 2024: 1-6 - [i12]Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini:
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication. CoRR abs/2401.04012 (2024) - [i11]Michael Rogenmoser, Alessandro Ottaviano, Thomas Benz, Robert Balas, Matteo Perotti, Angelo Garofalo, Luca Benini:
SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications. CoRR abs/2406.06546 (2024) - [i10]Matteo Perotti, Michele Raeber, Mattia Sinigaglia, Matheus A. Cavalcante, Davide Rossi, Luca Benini:
Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads. CoRR abs/2407.05447 (2024) - 2023
- [j1]Matteo Perotti, Matheus A. Cavalcante, Alessandro Ottaviano, Jiantao Liu, Luca Benini:
Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3732-3736 (2023) - [c7]Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini:
AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads. DATE 2023: 1-6 - [c6]MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David:
Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. ISCAS 2023: 1-5 - [i9]MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David:
Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. CoRR abs/2302.05996 (2023) - [i8]Angelo Garofalo, Yvan Tortorella, Matteo Perotti, Luca Valente, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti:
DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training. CoRR abs/2303.17954 (2023) - [i7]Matheus A. Cavalcante, Matteo Perotti, Samuel Riedel, Luca Benini:
Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency. CoRR abs/2309.10137 (2023) - [i6]Matteo Perotti, Matheus A. Cavalcante, Renzo Andri, Lukas Cavigelli, Luca Benini:
Ara2: Exploring Single- and Multi-Core Vector Processing with an Efficient RVV1.0 Compliant Open-Source Processor. CoRR abs/2311.07493 (2023) - [i5]Jannis Schönleber, Lukas Cavigelli, Renzo Andri, Matteo Perotti, Luca Benini:
Stella Nera: Achieving 161 TOp/s/W with Multiplier-free DNN Acceleration based on Approximate Matrix Multiplication. CoRR abs/2311.10207 (2023) - [i4]Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini:
Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV. CoRR abs/2311.10378 (2023) - 2022
- [c5]Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini:
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. ASAP 2022: 43-51 - [c4]Angelo Garofalo, Matteo Perotti, Luca Valente, Yvan Tortorella, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti:
Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training. ESSCIRC 2022: 273-276 - [c3]Matheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini:
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters. ICCAD 2022: 22:1-22:9 - [i3]Matheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini:
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters. CoRR abs/2207.07970 (2022) - [i2]Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini:
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design. CoRR abs/2210.08882 (2022) - [i1]Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini:
AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads. CoRR abs/2211.10409 (2022) - 2021
- [c2]Luca Bertaccini, Matteo Perotti, Stefan Mach, Pasquale Davide Schiavone, Florian Zaruba, Luca Benini:
Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores. ISCAS 2021: 1-5 - [c1]Matteo Perotti, Giuseppe Tagliavini, Stefan Mach, Luca Bertaccini, Luca Benini:
RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors. SAMOS 2021: 16-32
Coauthor Index
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