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ORCIDRoger Moussalli
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2010 – 2019
- 2017
[c12]Roger Moussalli:
Tradeoffs and Considerations in the Design of Accelerators for Database Applications. ICDE 2017: 1615- 2016
- [c11]Dajung Lee, Roger Moussalli, Sameh W. Asaad, Mudhakar Srivatsa:
Spatial Predicates Evaluation in the Geohash Domain Using Reconfigurable Hardware. FCCM 2016: 176-183 - 2015
- [j2]Roger Moussalli, Ildar Absalyamov, Marcos R. Vieira, Walid A. Najjar
, Vassilis J. Tsotras:
High performance FPGA and GPU complex pattern matching over spatio-temporal streams. GeoInformatica 19(2): 405-434 (2015) - [c10]Roger Moussalli, Mudhakar Srivatsa, Sameh W. Asaad:
Fast and Flexible Conversion of Geohash Codes to and from Latitude/Longitude Coordinates. FCCM 2015: 179-186 - 2014
- [j1]Roger Moussalli, Mariam Salloum, Robert J. Halstead, Walid A. Najjar, Vassilis J. Tsotras:
A study on parallelizing XML path filtering using accelerators. ACM Trans. Embed. Comput. Syst. 13(4): 93:1-93:28 (2014) - [c9]Andrew S. Cassidy, Rodrigo Alvarez-Icaza, Filipp Akopyan, Jun Sawada, John V. Arthur, Paul Merolla, Pallab Datta, Marc González Tallada, Brian Taba, Alexander Andreopoulos, Arnon Amir, Steven K. Esser, Jeff Kusnitz, Rathinakumar Appuswamy, Chuck Haymes, Bernard Brezzo, Roger Moussalli, Ralph Bellofatto, Christian W. Baks, Michael Mastro, Kai Schleupen, Charles E. Cox, Ken Inoue, Steven E. Millman, Nabil Imam, Emmett McQuinn, Yutaka Y. Nakamura, Ivan Vo, Chen Guok, Don Nguyen, Scott Lekuch, Sameh W. Asaad, Daniel J. Friedman, Bryan L. Jackson, Myron Flickner, William P. Risk, Rajit Manohar, Dharmendra S. Modha:
Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution. SC 2014: 27-38 - 2013
- [b1]Roger Moussalli:
Hardware Acceleration Of Database Applications. University of California, Riverside, USA, 2013 - [c8]Roger Moussalli, Walid A. Najjar, Xi Luo, Amna Khan:
A High Throughput No-Stall Golomb-Rice Hardware Decoder. FCCM 2013: 65-72 - [c7]Roger Moussalli, Bharat Sukhwani, Sameh W. Asaad:
FINPAGE: Generating high performance feed-specific parser circuits. GlobalSIP 2013: 1132 - [c6]Roger Moussalli, Marcos R. Vieira, Walid A. Najjar, Vassilis J. Tsotras:
Stream-Mode FPGA Acceleration of Complex Pattern Trajectory Querying. SSTD 2013: 201-222 - [c5]Ildar Absalyamov, Roger Moussalli, Vassilis J. Tsotras, Walid A. Najjar:
High-Performance XML Twig Filtering using GPUs. ADMS@VLDB 2013: 13-24 - 2011
- [c4]Mark Bucciero, John Paul Walters, Roger Moussalli, Shanyuan Gao, Matthew French:
The PowerPC 405 Memory Sentinel and Injection System. FCCM 2011: 154-161 - [c3]Roger Moussalli, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras:
Massively parallel XML twig filtering using dynamic programming on FPGAs. ICDE 2011: 948-959 - [c2]Roger Moussalli, Robert J. Halstead, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras:
Efficient XML Path Filtering Using GPUs. ADMS@VLDB 2011: 9-18 - 2010
- [c1]Roger Moussalli, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras:
Accelerating XML Query Matching through Custom Stack Generation on FPGAs. HiPEAC 2010: 141-155
Coauthor Index
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