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2020 – today
- 2022
[j21]S. Indrapriyadarsini
, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai:
Accelerating Symmetric Rank-1 Quasi-Newton Method with Nesterov's Gradient for Training Neural Networks. Algorithms 15(1): 6 (2022)- [c61]S. Indrapriyadarsini, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai:
On the Practical Robustness of the Nesterov's Accelerated Quasi-Newton Method. AAAI 2022: 12884-12885 - [c60]S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai:
A Stochastic Momentum Accelerated Quasi-Newton Method for Neural Networks (Student Abstract). AAAI 2022: 12973-12974 - 2021
- [i6]S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai:
A modified limited memory Nesterov's accelerated quasi-Newton. CoRR abs/2112.01327 (2021) - 2020
- [c59]S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai:
A Neural Network Approach to Analog Circuit Design Optimization using Nesterov's Accelerated Quasi-Newton Method. ISCAS 2020: 1 - [i5]S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Takeshi Kamio, Hideki Asai:
A Nesterov's Accelerated quasi-Newton method for Global Routing using Deep Reinforcement Learning. CoRR abs/2010.09465 (2020)
2010 – 2019
- 2019
- [c58]Sota Yasuda, Shahrzad Mahboubi, S. Indrapriyadarsini, Hiroshi Ninomiya, Hideki Asai:
A Stochastic Variance Reduced Nesterov's Accelerated Quasi-Newton Method. ICMLA 2019: 1874-1879 - [c57]S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai:
A Stochastic Quasi-Newton Method with Nesterov's Accelerated Gradient. ECML/PKDD (1) 2019: 743-760 - [c56]Shahrzad Mahboubi, S. Indrapriyadarsini, Hiroshi Ninomiya, Hideki Asai:
Momentum Acceleration of Quasi-Newton Training for Neural Networks. PRICAI (2) 2019: 268-281 - [i4]S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai:
An Adaptive Stochastic Nesterov Accelerated Quasi Newton Method for Training RNNs. CoRR abs/1909.03620 (2019) - [i3]S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai:
A Stochastic Quasi-Newton Method with Nesterov's Accelerated Gradient. CoRR abs/1909.03621 (2019) - [i2]Sota Yasuda, Shahrzad Mahboubi, S. Indrapriyadarsini, Hiroshi Ninomiya, Hideki Asai:
A Stochastic Variance Reduced Nesterov's Accelerated Quasi-Newton Method. CoRR abs/1910.07939 (2019) - [i1]S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai:
Implementation of a modified Nesterov's Accelerated quasi-Newton Method on Tensorflow. CoRR abs/1910.09158 (2019) - 2018
- [c55]S. Indrapriyadarsini, Shahrzad Mahboubi, Hiroshi Ninomiya, Hideki Asai:
Implementation of a Modified Nesterov's Accelerated Quasi-Newton Method on Tensorflow. ICMLA 2018: 1147-1154 - 2017
- [c54]Hideki Asai:
SI/PI/EMI simulation techniques and application to automotive electronic design issues. MIXDES 2017: 41-44 - 2014
- [j20]Hideki Asai:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(3): 725 (2014) - [c53]Takahiro Takasaki, Tadatoshi Sekine, Hideki Asai:
HIE-block latency insertion method for fast transient simulation of nonuniform multiconductor transmission lines. ASP-DAC 2014: 774-779 - 2013
- [c52]Tadatoshi Sekine, Hideki Asai:
Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network with through silicon via. ASP-DAC 2013: 7-12 - 2012
- [c51]Hiroki Kurobe, Tadatoshi Sekine, Hideki Asai:
Predictor-corrector latency insertion method for fast transient analysis of ill-constructed circuits. ASP-DAC 2012: 365-370 - 2010
- [j19]Yuji Okazaki, Takanori Uno, Hideki Asai:
An Optimization System with Parallel Processing for Reducing Common-Mode Current on Electronic Control Unit. IEICE Trans. Electron. 93-C(6): 827-834 (2010) - [j18]Takanori Uno, Kouji Ichikawa, Yuichi Mabuchi, Atsushi Nakamura, Yuji Okazaki, Hideki Asai:
An Approach for Practical Use of Common-Mode Noise Reduction Technique for In-Vehicle Electronic Equipment. IEICE Trans. Commun. 93-B(7): 1788-1796 (2010) - [c50]Shuichi Aono, Masaki Unno, Hideki Asai:
A novel FDTD algorithm based on alternating-direction explicit method with PML absorbing boundary condition. ASP-DAC 2010: 137-141 - [c49]Takayuki Watanabe, Hideki Asai:
Equivalent circuit modeling of multilayered power/ground planes for fast transient simulation. DATE 2010: 1153-1158
2000 – 2009
- 2009
- [j17]Tadatoshi Sekine, Hideki Asai:
CMOS Circuit Simulation Using Latency Insertion Method. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(10): 2546-2553 (2009) - 2008
- [j16]Yuya Nakazono, Hideki Asai:
Acceleration of ADI-FDTD Method by Gauss-Seidel Relaxation Approach. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2): 550-553 (2008) - [j15]Tadatoshi Sekine, Yuichi Tanji, Hideki Asai:
Matrix Order Reduction by Nodal Analysis Formulation and Relaxation-Based Fast Simulation for Power/Ground Plane. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(9): 2450-2455 (2008) - [j14]Yuichi Tanji, Hideki Asai, Masayoshi Oda, Yoshifumi Nishio, Akio Ushida:
Fast Simulation Technique of Plane Circuits via Two-Layer CNN-Based Modeling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3757-3762 (2008) - [c48]Yuichi Tanji, Takayuki Watanabe, Hideki Asai:
Generating stable and sparse reluctance/inductance matrix under insufficient conditions. ASP-DAC 2008: 164-169 - 2007
- [j13]Takayuki Watanabe, Yuichi Tanji, Hidemasa Kubota, Hideki Asai:
Fast Transient Simulation of Power Distribution Networks Containing Dispersion Based on Parallel-Distributed Leapfrog Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(2): 388-397 (2007) - [c47]Akira Tsuzaki, Toshio Unno, Yuichi Tanji, Hideki Asai:
A fast transient simulation based on Model Order Reduction and RLCG-MNA formulation. ECCTD 2007: 775-778 - [c46]Yuya Nakazono, Hideki Asai:
Application of Relaxation-Based Technique to ADI-FDTD Method and Its Estimation. ISCAS 2007: 1489-1492 - 2006
- [j12]Hidemasa Kubota, Yuichi Tanji, Takayuki Watanabe, Hideki Asai:
An Enhanced Time-Domain Circuit Simulation Technique Based on LIM. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(5): 1505-1506 (2006) - [c45]Takayuki Watanabe, Yuichi Tanji, Hidemasa Kubota, Hideki Asai:
Parallel-distributed time-domain circuit simulation of power distribution networks with frequency-dependent parameters. ASP-DAC 2006: 832-837 - [c44]Hiroshi Ninomiya, Kimihiko Numayama, Hideki Asai:
Two-staged Tabu Search for Floorplan Problem Using O-Tree Representation. IEEE Congress on Evolutionary Computation 2006: 718-724 - [c43]Takafumi Yamamoto, Tsutomu Suzuki, Hideki Asai:
Concurrent Design of Delta-Sigma Modulator Using Behavioral Modeling and Simulation with the Verilog-A. CICC 2006: 341-344 - [c42]Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai:
Large scale RLC circuit analysis using RLCG-MNA formulation. DATE 2006: 45-46 - [c41]Yuichi Tanji, Hideki Asai, Masayoshi Oda, Yoshifumi Nishio, Akio Ushida:
Fast timing analysis of plane circuits via two-layer CNN-based modeling. ISCAS 2006 - [c40]Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai:
Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA Formulation. ISQED 2006: 393-400 - 2005
- [j11]Yuichi Tanji, Masaya Suzuki, Takayuki Watanabe, Hideki Asai:
New Criteria of Selective Orthogonal Matrix Least-Squares Method for Macromodeling Multiport Networks Characterized by Sampled Data. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(2): 524-532 (2005) - [c39]Hirokazu Yamagishi, Hiroshi Ninomiya, Hideki Asai:
Three dimensional module packing by simulated annealing. Congress on Evolutionary Computation 2005: 1069-1074 - [c38]Hidemasa Kubota, Yuichi Tanji, Takayuki Watanabe, Hideki Asai:
Generalized method of the time-domain circuit simulation based on LIM with MNA formulation. CICC 2005: 289-292 - [c37]Yuichi Tanji, Hiroo Sekiya, Hideki Asai:
Optimization procedure of class E amplifiers using SPICE. ECCTD 2005: 133-136 - [c36]Hirofumi Suzuki, Hidemasa Kubota, Takayuki Watanabe, Hideki Asai:
Interconnect simulation using FDTD method with variable mesh size technique. ECCTD 2005: 225-228 - [c35]Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Modified hybrid reduction technique for the simulation of linear/nonlinear mixed circuits. ISCAS (5) 2005: 4903-4906 - [c34]Takayuki Watanabe, Hideki Asai:
Modeling of power distribution networks with signal lines for SPICE simulators. ISCAS (6) 2005: 5774-5777 - 2004
- [c33]Yuichi Tanji, Hideki Asai:
Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects. DAC 2004: 810-813 - [c32]Takashi Mine, Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits. DATE 2004: 1327-1333 - 2003
- [j10]Takayuki Watanabe, Hideki Asai:
A Framework for Macromodeling and Mixed-Mode Simulation of Circuits/Interconnects and Electromagnetic Radiations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(2): 252-261 (2003) - [j9]Shashidhar Tantry, Yasuyuki Hiraku, Takao Oura, Teru Yoneyama, Hideki Asai:
A Low Voltage Floating Resistor Circuit Having Both Positive and Negative Resistance Values. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(2): 335-341 (2003) - [j8]Masahiro Yoshida, Takeshi Kamio, Hideki Asai:
Face Image Recognition by 2-Dimensional Discrete Walsh Transform and Multi-Layer Neural Network. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(10): 2623-2627 (2003) - [c31]Yuichi Tanji, Masaya Suzuki, Takayuki Watanabe, Hideki Asai:
Behavioral modeling of EM devices by selective orthogonal matrix least-squares method. ASP-DAC 2003: 184-188 - [c30]Takayuki Watanabe, Hideki Asai:
Analysis of PCB interconnects using electromagnetic reduction technique. ISCAS (3) 2003: 498-501 - 2002
- [j7]Kenichi Suzuki, Mitsuhiro Takeda, Atsushi Kamo, Hideki Asai:
A Novel Application of Verilog-A to Modeling and Simulation of High-Speed Interconnects in Time/Frequency Transform-Domain. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(2): 395-398 (2002) - [j6]Takao Oura, Teru Yoneyama, Shashidhar Tantry, Hideki Asai:
A CMOS Floating Resistor Circuit Having Both Positive and Negative Resistance Values. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(2): 399-402 (2002) - [j5]Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
An Efficient Simulator for Multiport Interconnects with Model Order Reduction Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(6): 1214-1219 (2002) - [j4]Tsutomu Suzuki, Takao Oura, Teru Yoneyama, Hideki Asai:
Design and Simulation of 4Q-Multiplier Using Linear and Saturation Regions of MOSFET Complementally. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(6): 1242-1248 (2002) - [c29]Shashidhar Tantry, Takao Oura, Teru Yoneyama, Hideki Asai:
A low voltage floating resistor having positive and negative resistance values. APCCAS (1) 2002: 347-350 - [c28]I. Hattori, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Optimal placement of decoupling capacitors on PCB using Poynting vectors obtained by FDTD method. ISCAS (5) 2002: 29-32 - [c27]Hidemasa Kubota, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Noise analysis of power/ground planes on PCB by SPICE-like simulator with model order reduction technique. ISCAS (5) 2002: 649-552 - [c26]Takao Oura, Teru Yoneyama, Shashidhar Tantry, Hideki Asai:
A threshold voltage independent floating resistor circuit exhibiting both positive and negative resistance values. ISCAS (3) 2002: 739-742 - 2001
- [j3]Shinsuke Manabe, Hideki Asai:
A Neuro-Based Optimization Algorithm for Tiling Problems with Rotation. Neural Process. Lett. 13(3): 267-275 (2001) - [c25]Masaya Suzuki, Hirofumi Miyashita, Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
High-speed interconnect simulation using MIMO type of adaptive least square method. ISCAS (5) 2001: 327-330 - [c24]Shashidhar Tantry, Teru Yoneyama, Hideki Asai:
Two floating resistor circuits and their applications to synaptic weights in analog neural networks. ISCAS (1) 2001: 564-567 - [c23]Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Simulation for the optimal placement of decoupling capacitors on printed circuit board. ISCAS (3) 2001: 727-730 - 2000
- [c22]Masahiro Yoshida, Hideki Asai, Takeshi Kamio:
Neuro-Based Human-Face Recognition with 2-Dimensional Discrete Walsh Transform. IJCNN (3) 2000: 315-319 - [c21]Teru Yoneyama, Hideki Asai, Hiroshi Ninomiya:
Design Method of Limit Cycle Generator by Hysteresis Neural Networks. IJCNN (3) 2000: 500-505
1990 – 1999
- 1999
- [c20]Teru Yoneyama, Hiroshi Ninomiya, Hideki Asai:
Design method of neural networks for limit cycle generator. IJCNN 1999: 2402-2405 - [c19]Shinsuke Manabe, Hideki Asai:
A neuro-based optimization algorithm for tiling problems with rotation. IJCNN 1999: 3750-3753 - [c18]Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Expanded GMC for transient analysis of transmission line networks. ISCAS (6) 1999: 33-36 - [c17]Takayuki Watanabe, Hideki Asai:
Efficient synthesis technique of time-domain models for interconnects having 3-D structures based on FDTD method. ISCAS (6) 1999: 266-269 - 1998
- [c16]Takayuki Watanabe, Hideki Asai:
Transient analysis for high-speed interconnect networks based on AWE and delay evaluation technique. ICECS 1998: 103-106 - [c15]Atsushi Kamo, Hiroshi Ninomiya, Teru Yoneyama, Hideki Asai:
Neural network simulator for spatiotemporal pattern analysis. ICECS 1998: 109-112 - [c14]Hiroshi Sagesaka, Hisashi Irii, Hideki Asai:
SPADE : analog/digital mixed signal simulator with analog hardware description language. ICECS 1998: 517-520 - 1997
- [c13]Hiroyuki Yamamoto, Takeshi Nakayama, Hiroshi Ninomiya, Hideki Asai:
Application of neuro-based optimization algorithm to three dimensional cylindric puzzles. ICNN 1997: 1246-1250 - 1996
- [c12]Takayuki Watanabe, Hideki Asai:
DESIRE3T+: waveform relaxation-based simulator for coupled lossy transmission lines circuits. ICECS 1996: 370-373 - [c11]Hideki Asai, Takeshi Nakayama, Hiroshi Ninomiya:
Tiling algorithm with fitting violation function for analog neural array. ICNN 1996: 565-570 - [c10]Takeshi Kamio, Hiroshi Ninomiya, Hideki Asai:
Design and implementation of neuro-based discrete Walsh transform processor. ICNN 1996: 926-931 - [c9]Hiroshi Ninomtya, Kunitaka Egawa, Takeshi Kamio, Hideki Asai:
Design and implementation of neural network logic circuits with global convergence. ICNN 1996: 980-985 - 1995
- [c8]Hideki Asai, Katsuaki Onodera, Takeshi Kamio, Hiroshi Ninomiya:
A study of Hopfield neural networks with external noises. ICNN 1995: 1584-1589 - [c7]Hiroshi Ninomiya, Kazumichi Sato, Takeshi Nakayama, Hideki Asai:
Neural network approach to traveling salesman problem based on hierarchical city adjacency. ICNN 1995: 2626-2631 - [c6]Takeshi Kamio, Hiroshi Ninomiya, Hideki Asai:
Convergence of Hopfield Neural Network for Orthogonal Transformation. ISCAS 1995: 493-496 - [c5]Hiroshi Ninomiya, Hideki Asai:
Orthogonalized Steepest Descent Method for Solving Nonlinear Equations. ISCAS 1995: 740-743 - 1994
- [c4]Takeshi Senoo, Hiroaki Makino, Hideki Asai:
Relaxation-Based Steady-State Analysis of Single- and Multi-Conductor Transmission Lines in Frequency Domain. ISCAS 1994: 5-8 - [c3]Masakatsu Nishigaki, Nobuyuki Tanaka, Hideki Asai:
Mixed Mode Circuit Simulator SPLIT2.1 using Dynamic Network Separation and Selective Trace. ISCAS 1994: 9-12 - [c2]Masaki Ishida, Koichi Hayashi, Masakatsu Nishigaki, Hideki Asai:
Iterated Timing Analysis with Dynamic Partitioning Technique for Bipolar Transistor Circuits. ISCAS 1994: 411-414 - [c1]Vijaya Gopal Bandi, Hideki Asai:
Transient Simulation of Coupled Lossy Interconnects by Window Partitioning Technique. ISCAS 1994: 419-422
1980 – 1989
- 1987
- [j2]Hideki Asai, Mitsuo Asai, Mamoru Tanaka:
Special parallel processor for lu decomposition of a large-scale sparse matrix. Syst. Comput. Jpn. 18(6): 89-99 (1987) - 1985
- [j1]Hideki Asai, Shinsaku Mori:
Network analysis by hierarchical tearing method. Syst. Comput. Jpn. 16(6): 59-67 (1985)
Coauthor Index
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