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2010 – 2019
- 2018
[j46]Yibo Lin
, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan:
MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1237-1250 (2018)- [c88]Charles J. Alpert, Wing-Kai Chow, Kwangsoo Han, Andrew B. Kahng, Zhuo Li, Derong Liu, Sriram Venkatesh:
Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees. ISPD 2018: 10-17 - 2017
- [j45]Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan:
Stitch aware detailed placement for multiple E-beam lithography. Integr. 58: 47-54 (2017) - [c87]Charles J. Alpert:
Modern Challenges in Constructing Clocks. ISPD 2017: 65 - 2016
- [j44]Vijaykrishnan Narayanan, Charles J. Alpert, Sara Dailey:
Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3): 345 (2016) - [c86]Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan:
Stitch aware detailed placement for multiple e-beam lithography. ASP-DAC 2016: 186-191 - [c85]Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan:
MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes. ICCAD 2016: 7 - 2015
- [j43]Vijaykrishnan Narayanan, Charles J. Alpert, Sara Dailey:
Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(1): 1 (2015) - [j42]Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Yibo Lin, Zhuo Li, Charles J. Alpert, David Z. Pan:
Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 726-739 (2015) - 2014
- [j41]Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar:
Techniques for scalable and effective routability evaluation. ACM Trans. Design Autom. Electr. Syst. 19(2): 17:1-17:37 (2014) - [c84]Nancy Y. Zhou, Phillip J. Restle, Joseph N. Palumbo, Joseph N. Kozhaya, Haifeng Qian, Zhuo Li, Charles J. Alpert, Cliff C. N. Sze:
Pacman: driving nonuniform clock grid loads for low-skew robust clock network. SLIP 2014: 3:1-3:5 - 2013
- [j40]Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan:
Structure-Aware Placement Techniques for Designs With Datapaths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2): 228-241 (2013) - [c83]Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert:
Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths. ASP-DAC 2013: 350-355 - [c82]Wen-Hao Liu, Yaoguang Wei, Cliff C. N. Sze, Charles J. Alpert, Zhuo Li, Yih-Lang Li, Natarajan Viswanathan:
Routing congestion estimation with real design constraints. DAC 2013: 92:1-92:8 - [c81]Yaoguang Wei, Zhuo Li, Cliff C. N. Sze, Shiyan Hu, Charles J. Alpert, Sachin S. Sapatnekar:
CATALYST: planning layer directives for effective design closure. DATE 2013: 1873-1878 - [c80]Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert:
ICCAD-2013 CAD contest in placement finishing and benchmark suite. ICCAD 2013: 268-270 - [c79]Samuel I. Ward, Natarajan Viswanathan, Nancy Y. Zhou, Cliff C. N. Sze, Zhuo Li, Charles J. Alpert, David Z. Pan:
Clock power minimization using structured latch templates and decision tree induction. ICCAD 2013: 599-606 - 2012
- [c78]Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Cliff C. N. Sze, Natarajan Viswanathan, Nancy Y. Zhou:
Guiding a physical design closure system to produce easier-to-route designs with more predictable timing. DAC 2012: 465-470 - [c77]Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar:
GLARE: global and local wiring aware routability evaluation. DAC 2012: 768-773 - [c76]Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei:
The DAC 2012 routability-driven placement contest and benchmark suite. DAC 2012: 774-782 - [c75]Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert:
WRIP: logic restructuring techniques for wirelength-driven incremental placement. ACM Great Lakes Symposium on VLSI 2012: 327-332 - [c74]Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Chin Ngai Sze, Natarajan Viswanathan, Samuel I. Ward:
Placement: Hot or Not? ICCAD 2012: 283-290 - [c73]Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei:
ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite. ICCAD 2012: 345-348 - [c72]Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan:
Keep it straight: teaching placement how to better handle designs with datapaths. ISPD 2012: 79-86 - [c71]Myung-Chul Kim, Natarajan Viswanathan, Charles J. Alpert, Igor L. Markov, Shyam Ramji:
MAPLE: multilevel adaptive placement for mixed-size designs. ISPD 2012: 193-200 - 2011
- [j39]David A. Papa, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Natarajan Viswanathan, Gi-Joon Nam, Igor L. Markov:
Physical Synthesis with Clock-Network Optimization for Large Systems on Chips. IEEE Micro 31(4): 51-62 (2011) - [j38]Nancy Ying Zhou, Charles J. Alpert, Zhuo Li, Cliff N. Sze, Louise Trevillyan:
Shedding Physical Synthesis Area Bloat. VLSI Design 2011: 503025:1-503025:10 (2011) - [c70]Samuel I. Ward, David A. Papa, Zhuo Li, Cliff N. Sze, Charles J. Alpert, Earl E. Swartzlander Jr.:
Quantifying academic placer performance on custom designs. ISPD 2011: 91-98 - [c69]Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Gi-Joon Nam, Jarrod A. Roy:
The ISPD-2011 routability-driven placement contest and benchmark suite. ISPD 2011: 141-146 - 2010
- [j37]David A. Papa, Michael D. Moffitt, Charles J. Alpert, Igor L. Markov:
Speeding Up Physical Synthesis with Transactional Timing Analysis. IEEE Des. Test Comput. 27(5): 14-25 (2010) - [c68]Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li, Gi-Joon Nam, Charles B. Winn:
Detecting tangled logic structures in VLSI netlists. DAC 2010: 603-608 - [c67]Taraneh Taghavi, Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Andrew D. Huber, Shyam Ramji:
New placement prediction and mitigation techniques for local routing congestion. ICCAD 2010: 621-624 - [c66]Yi-Lin Chuang, Gi-Joon Nam, Charles J. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan:
Design-hierarchy aware mixed-size placement for routability optimization. ICCAD 2010: 663-668 - [c65]Charles J. Alpert, Zhuo Li, Michael D. Moffitt, Gi-Joon Nam, Jarrod A. Roy, Gustavo E. Téllez:
What makes a design difficult to route. ISPD 2010: 7-12 - [c64]Zhuo Li, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Nancy Ying Zhou:
Ultra-fast interconnect driven cell cloning for minimizing critical path delay. ISPD 2010: 75-82 - [c63]Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy, Zhuo Li, Charles J. Alpert, Shyam Ramji, Chris Chu:
ITOP: integrating timing optimization within placement. ISPD 2010: 83-90
2000 – 2009
- 2009
- [j36]Shiyan Hu, Zhuo Li, Charles J. Alpert:
A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment. IEEE Trans. Circuits Syst. II Express Briefs 56-II(7): 580-584 (2009) - [c62]Shiyan Hu, Zhuo Li, Charles J. Alpert:
A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion. DAC 2009: 424-429 - [c61]Jarrod A. Roy, Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov:
CRISP: Congestion reduction by iterated spreading during placement. ICCAD 2009: 357-362 - [c60]Cliff N. Sze, Phillip J. Restle, Gi-Joon Nam, Charles J. Alpert:
Ispd2009 clock network synthesis contest. ISPD 2009: 149-150 - [c59]Shiyan Hu, Zhuo Li, Charles J. Alpert:
A faster approximation scheme for timing driven minimum cost layer assignment. ISPD 2009: 167-174 - 2008
- [j35]David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov:
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2156-2168 (2008) - [c58]Michael D. Moffitt, David A. Papa, Zhuo Li, Charles J. Alpert:
Path smoothing via discrete optimization. DAC 2008: 724-727 - [c57]Shiyan Hu, Zhuo Li, Charles J. Alpert:
A polynomial time approximation scheme for timing constrained minimum cost layer assignment. ICCAD 2008: 112-115 - [c56]Tao Luo, David A. Papa, Zhuo Li, Chin Ngai Sze, Charles J. Alpert, David Z. Pan:
Pyramids: an efficient computational geometry-based approach for timing-driven placement. ICCAD 2008: 204-211 - [c55]David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov:
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. ISPD 2008: 2-9 - [c54]Zhuo Li, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia:
Fast interconnect synthesis with layer assignment. ISPD 2008: 71-77 - [e4]Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar:
Handbook of Algorithms for Physical Design Automation. Auerbach Publications 2008, ISBN 978-0-8493-7242-1 [contents] - [r2]Charles J. Alpert, Nathaniel Hieter, Arjen Mets, Ruchir Puri, Lakshmi N. Reddy, Haoxing Ren, Louise Trevillyan:
Placement-Driven Synthesis Design Closure Tool. Handbook of Algorithms for Physical Design Automation 2008 - [r1]Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar:
Introduction to Physical Design. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [j34]Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz:
Techniques for Fast Physical Synthesis. Proc. IEEE 95(3): 573-599 (2007) - [j33]Chin Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi:
Path-Based Buffer Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1346-1355 (2007) - [j32]Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin Ngai Sze:
Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 2009-2022 (2007) - [j31]Haoxing Ren, David Z. Pan, Charles J. Alpert, Paul G. Villarrubia, Gi-Joon Nam:
Diffusion-Based Placement Migration With Application on Legalization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12): 2158-2172 (2007) - [c53]Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia:
Hippocrates: First-Do-No-Harm Detailed Placement. ASP-DAC 2007: 141-146 - [c52]Shrirang K. Karandikar, Charles J. Alpert, Mehmet Can Yildiz, Paul Villarrubia, Stephen T. Quay, T. Mahmud:
Fast Electrical Correction Using Resizing and Buffering. ASP-DAC 2007: 553-558 - [c51]Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu:
RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. DAC 2007: 453-458 - [c50]Charles J. Alpert, Chris C. N. Chu, Paul G. Villarrubia:
The coming of age of physical synthesis. ICCAD 2007: 246-249 - [c49]Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi:
Probabilistic Congestion Prediction with Partial Blockages. ISQED 2007: 841-846 - [c48]Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz:
The nuts and bolts of physical synthesis. SLIP 2007: 89-94 - [p1]Gi-Joon Nam, Charles J. Alpert, Paul G. Villarrubia:
ISPD 2005/2006 Placement Benchmarks. Modern Circuit Placement 2007: 3-12 - 2006
- [j30]Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng:
A Fast Hierarchical Quadratic Placement Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 678-691 (2006) - [j29]Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze:
Accurate estimation of global buffer delay within a floorplan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1140-1145 (2006) - [c47]Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze:
Fast algorithms for slew constrained minimum cost buffering. DAC 2006: 308-313 - [c46]Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang:
Timing-driven Steiner trees are (practically) free. DAC 2006: 389-392 - 2005
- [c45]Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi:
Making fast buffer insertion even faster via approximation techniques. ASP-DAC 2005: 13-18 - [c44]Charles J. Alpert, Gi-Joon Nam, Paul Villarribua, Mehmet Can Yildiz:
Placement stability metrics. ASP-DAC 2005: 1144-1147 - [c43]Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi:
Path based buffer insertion. DAC 2005: 509-514 - [c42]Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia:
Diffusion-based placement migration. DAC 2005: 515-520 - [c41]Tao Luo, Haoxing Ren, Charles J. Alpert, David Zhigang Pan:
Computational geometry based placement migration. ICCAD 2005: 41-47 - [c40]Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert:
Practical techniques to reduce skew and its variations in buffered clock networks. ICCAD 2005: 592-596 - [c39]Rajeev R. Rao, David T. Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif:
An efficient surface-based low-power buffer insertion algorithm. ISPD 2005: 86-93 - [c38]Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia:
A semi-persistent clustering technique for VLSI circuit placement. ISPD 2005: 200-207 - [c37]Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz:
The ISPD2005 placement contest and benchmark suite. ISPD 2005: 216-220 - 2004
- [j28]Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay:
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 136-141 (2004) - [j27]Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert:
A delay metric for RC circuits based on the Weibull distribution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(3): 443-447 (2004) - [j26]Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan:
Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 509-516 (2004) - [j25]Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze:
Porosity-aware buffered Steiner tree construction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 517-526 (2004) - [j24]Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan:
Closed-form delay and slew metrics made easy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1661-1669 (2004) - [c36]Cliff C. N. Sze, Jiang Hu, Charles J. Alpert:
A place and route aware buffered Steiner tree construction. ASP-DAC 2004: 355-360 - [c35]Weiping Shi, Zhuo Li, Charles J. Alpert:
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost. ASP-DAC 2004: 609-614 - [c34]Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay:
Fast and flexible buffer trees that navigate the physical layout environment. DAC 2004: 24-29 - [c33]Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze:
Accurate estimation of global buffer delay within a floorplan. ICCAD 2004: 706-711 - [c32]Charles J. Alpert, Milos Hrkic, Stephen T. Quay:
A fast algorithm for identifying good buffer insertion candidate locations. ISPD 2004: 47-52 - [e3]Charles J. Alpert, Patrick Groeneveld:
Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004. ACM 2004, ISBN 1-58113-817-2 [contents] - 2003
- [j23]Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky:
Minimum buffered routing with bounded capacitive load for slew rate and reliability control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 241-253 (2003) - [j22]Charles J. Alpert, Sachin S. Sapatnekar:
Guest editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 385-386 (2003) - [j21]Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham:
Buffer insertion with adaptive blockage avoidance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 492-498 (2003) - [j20]Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia:
A practical methodology for early buffer and wire resource allocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 573-583 (2003) - [j19]Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia:
Effective free space management for cut-based placement via analytical constraint generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10): 1343-1353 (2003) - [j18]Soha Hassoun, Charles J. Alpert:
Optimal path routing in single- and multiple-clock domain systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11): 1580-1588 (2003) - [c31]Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan:
Delay and slew metrics using the lognormal distribution. DAC 2003: 382-385 - [c30]Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan:
Closed form expressions for extending step delay and slew metrics to ramp inputs. ISPD 2003: 24-31 - [c29]Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay:
Porosity aware buffered steiner tree construction. ISPD 2003: 158-165 - [e2]Massoud Pedram, Charles J. Alpert:
Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003. ACM 2003, ISBN 1-58113-650-1 [contents] - 2002
- [j17]Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert:
Probability-driven routing in a datapath environment. Integr. 31(2): 159-182 (2002) - [j16]Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay:
Correction to "interconnect synthesis without wire tapering". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(4): 497-497 (2002) - [c28]Soha Hassoun, Charles J. Alpert, Meera Thiagarajan:
Optimal buffered routing path constructions for single and multiple clock domain systems. ICCAD 2002: 247-253 - [c27]Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert:
A delay metric for RC circuits based on the Weibull distribution. ICCAD 2002: 620-624 - [c26]Charles J. Alpert, Gi-Joon Nam, Paul Villarrubia:
Free space management for cut-based placement. ICCAD 2002: 746-751 - [c25]Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham:
Buffer insertion with adaptive blockage avoidance. ISPD 2002: 92-97 - [c24]Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay:
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ISPD 2002: 104-109 - [c23]Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan:
PERI: a technique for extending delay and slew metrics to ramp inputs. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 57-62 - [e1]David P. LaPotin, Charles J. Alpert, John Lillis:
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002. ACM 2002, ISBN 1-58113-526-2 [contents] - 2001
- [j15]Phillip J. Restle, Timothy G. McNamara, David A. Webber, Peter J. Camporese, Kwok F. Eng, Keith A. Jenkins, David H. Allen, Michael J. Rohn, Michael P. Quaranta, David W. Boerstler, Charles J. Alpert, Craig A. Carter, Roger N. Bailey, John G. Petrovick, Byron L. Krauter, Bradley D. McCredie:
A clock distribution network for microprocessors. IEEE J. Solid State Circuits 36(5): 792-799 (2001) - [j14]Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay:
Interconnect synthesis without wire tapering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 90-104 (2001) - [j13]Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar:
Steiner tree optimization for buffers, blockages, and bays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(4): 556-562 (2001) - [j12]Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap:
RC delay metrics for performance optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5): 571-582 (2001) - [c22]Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia:
A Practical Methodology for Early Buffer and Wire Resource Allocation. DAC 2001: 189-194 - [c21]Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky:
Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control. ICCAD 2001: 408- - [c20]Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar:
Steiner tree optimization for buffers. Blockages and bays. ISCAS (5) 2001: 399-402 - [c19]Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia:
Buffered Steiner trees for difficult instances. ISPD 2001: 4-9 - 2000
- [j11]Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Hypergraph partitioning with fixed vertices [VLSI CAD]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2): 267-272 (2000) - [c18]Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan:
An "Effective" Capacitance Based Delay Metric for RC Interconnect. ICCAD 2000: 229-234 - [c17]Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap:
A two moment RC delay metric for performance optimization. ISPD 2000: 69-74 - [c16]Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert:
Datapath routing based on a decongestion metric. ISPD 2000: 122-127
1990 – 1999
- 1999
- [j10]Charles J. Alpert, Andrew B. Kahng, So-Zen Yao:
Spectral Partitioning with Multiple Eigenvectors. Discret. Appl. Math. 90(1-3): 3-26 (1999) - [j9]Charles J. Alpert, Anirudh Devgan, Stephen T. Quay:
Buffer insertion for noise and delay optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11): 1633-1645 (1999) - [j8]Charles J. Alpert, Andrew E. Caldwell, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, M. S. Moroz:
Analytical Engines are Unnecessary in Top-down Partitioning-based Placement. VLSI Design 10(1): 99-116 (1999) - [c15]Charles J. Alpert, Anirudh Devgan, Stephen T. Quay:
Buffer Insertion with Accurate Gate and Interconnect Delay Computation. DAC 1999: 479-484 - [c14]Charles J. Alpert, Anirudh Devgan, Stephen T. Quay:
Is wire tapering worthwhile? ICCAD 1999: 430-436 - [c13]Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Partitioning with terminals: a "new" problem and new benchmarks. ISPD 1999: 151-157 - 1998
- [j7]Charles J. Alpert, Tony F. Chan, Andrew B. Kahng, Igor L. Markov, Pep Mulet:
Faster minimization of linear wirelength for global placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(1): 3-13 (1998) - [j6]Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng:
Multilevel circuit partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8): 655-667 (1998) - [c12]Charles J. Alpert, Anirudh Devgan, Stephen T. Quay:
Buffer Insertion for Noise and Delay Optimization. DAC 1998: 362-367 - [c11]Charles J. Alpert:
The ISPD98 circuit benchmark suite. ISPD 1998: 80-85 - 1997
- [c10]Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng:
Multilevel Circuit Partitioning. DAC 1997: 530-533 - [c9]Charles J. Alpert, Anirudh Devgan:
Wire Segmenting for Improved Buffer Insertion. DAC 1997: 588-593 - [c8]Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Igor L. Markov, Kenneth Yan:
Quadratic Placement Revisited. DAC 1997: 752-757 - [c7]Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, Pep Mulet, Kenneth Yan:
Faster minimization of linear wirelength for global placement. ISPD 1997: 4-11 - 1996
- [j5]Charles J. Alpert, Andrew B. Kahng:
A general framework for vertex orderings with applications to circuit clustering. IEEE Trans. Very Large Scale Integr. Syst. 4(2): 240-246 (1996) - 1995
- [j4]Charles J. Alpert, Andrew B. Kahng:
Recent directions in netlist partitioning: a survey. Integr. 19(1-2): 1-81 (1995) - [j3]Charles J. Alpert, T. C. Hu, Dennis J.-H. Huang, Andrew B. Kahng, David R. Karger:
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(7): 890-896 (1995) - [j2]Charles J. Alpert, Andrew B. Kahng:
Multiway partitioning via geometric embeddings, orderings, and dynamic programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(11): 1342-1358 (1995) - [c6]Charles J. Alpert, So-Zen Yao:
Spectral Partitioning: The More Eigenvectors, The Better. DAC 1995: 195-200 - 1994
- [j1]Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh:
On the Minimum Density Interconnection Tree Problem. VLSI Design 2(2): 157-169 (1994) - [c5]Charles J. Alpert, Andrew B. Kahng:
Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming. DAC 1994: 652-657 - [c4]Charles J. Alpert, Andrew B. Kahng:
A general framework for vertex orderings, with applications to netlist clustering. ICCAD 1994: 63-67 - 1993
- [c3]Charles J. Alpert, Andrew B. Kahng:
Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning. DAC 1993: 743-748 - [c2]Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh:
Minimum Density Interconneciton Trees. ISCAS 1993: 1865-1868 - [c1]Charles J. Alpert, T. C. Hu, Jen-Hsin Huang, Andrew B. Kahng:
A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing. ISCAS 1993: 1869-1872
Coauthor Index
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