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2020 – today
- 2022
[c3]Ofer Geva, Christopher J. Berry, Robert J. Sonnelitter, David Wolpert, Adam Collura, Thomas Strach, Di Phan, Cédric Lichtenau, Alper Buyuktosunoglu, Hubert Harrer, Jeffrey A. Zitz, Chad Marquart, Douglas Malone, Tobias Webel, Adam Jatkowski, John Isakson, Dina Hamid, Mark Cichanowski, Michael Romain, Faisal Hasan, Kevin Williams, Jesse Surprise, Chris Cavitt, Mark Cohen:
IBM Telum: a 16-Core 5+ GHz DCM. ISSCC 2022: 46-48
2010 – 2019
- 2015
- [j10]Wiren Dale Becker
, Hubert Harrer, Andreas Huber, W. L. Brodsky, R. Krabbenhoft, M. A. Cracraft, Dierk Kaller, Gregory R. Edlund, Thomas Strach:
Electronic packaging of the IBM z13 processor drawer. IBM J. Res. Dev. 59(4/5) (2015) - 2014
- [j9]James D. Warnock, Yuen H. Chan, Hubert Harrer, Sean M. Carey, Gerard Salem, Doug Malone, Ruchir Puri, Jeffrey A. Zitz, Adam Jatkowski, Gerald Strevig, Ayan Datta, Anne Gattiker, Aditya Bansal, Guenter Mayer, Yiu-Hing Chan, Mark D. Mayo, David L. Rude, Leon J. Sigal, Thomas Strach, Howard H. Smith, Huajun Wen, Pak-kin Mak, Chung-Lung Kevin Shum, Donald W. Plass, Charles F. Webb:
Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module. IEEE J. Solid State Circuits 49(1): 9-18 (2014) - 2013
- [c2]James D. Warnock, Yuen H. Chan, Hubert Harrer, David L. Rude, Ruchir Puri, Sean M. Carey, Gerard Salem, Guenter Mayer, Yiu-Hing Chan, Mark D. Mayo, Adam Jatkowski, Gerald Strevig, Leon J. Sigal, Ayan Datta, Anne Gattiker, Aditya Bansal, Doug Malone, Thomas Strach, Huajun Wen, Pak-kin Mak, Chung-Lung Kevin Shum, Donald W. Plass, Charles F. Webb:
5.5GHz system z microprocessor and multi-chip module. ISSCC 2013: 46-47 - 2012
- [j8]Thomas Strach, Frank E. Bosco, Kenneth L. Christian, Kevin R. Covi, Martin Eckert, Gregory R. Edlund, Roland Frech, Hubert Harrer, Andreas Huber, Dierk Kaller, Martin Kindscher, A. Z. Muszynski, G. A. Peterson, Claudio Siviero, Jochen Supper, Otto A. Torreiter, Thomas-Michael Winkel:
Electronic packaging of the IBM System z196 enterprise-class server processor cage. IBM J. Res. Dev. 56(1): 2 (2012)
2000 – 2009
- 2009
- [j7]Thomas-Michael Winkel, Hubert Harrer, Dierk Kaller, Jochen Supper, Daniel M. Dreps, Kenneth L. Christian, D. Cosmadelis, Tingdong Zhou, Thomas Strach, J. Ludwig, David L. Edwards:
Packaging design challenges of the IBM System z10 Enterprise Class server. IBM J. Res. Dev. 53(1): 10 (2009) - 2007
- [j6]Hubert Harrer, Daniel M. Dreps, Thomas-Michael Winkel, Wolfgang Scholz, Bao G. Truong, Andreas Huber, Tingdong Zhou, Kenneth L. Christian, Gary F. Goth:
High-speed interconnect and packaging design of the IBM System z9 processor cage. IBM J. Res. Dev. 51(1/2): 37-52 (2007) - 2004
- [j5]Thomas-Michael Winkel, Wiren Dale Becker, Hubert Harrer, Harald Pross, Dierk Kaller, Bernd Garben, Bruce J. Chamberlin, Scott A. Kuppinger:
First- and second-level packaging of the z990 processor cage. IBM J. Res. Dev. 48(3-4): 379-394 (2004) - 2002
- [j4]Hubert Harrer, Harald Pross, Thomas-Michael Winkel, Wiren Dale Becker, Herb I. Stoller, Masakazu Yamamoto, Shinji Abe, Bruce J. Chamberlin, George A. Katopis:
First- and second-level packaging for the IBM eServer z900. IBM J. Res. Dev. 46(4-5): 397-420 (2002)
1990 – 1999
- 1994
- [c1]Hubert Harrer, Josef A. Nossek, Tamás Roska, Leon O. Chua:
A Current-Mode DTCNN Universal Chip . ISCAS 1994: 135-138 - 1993
- [j3]Hubert Harrer, Zbigniew Galias, Josef A. Nossek:
On the convergence of discrete-time neural networks. Int. J. Circuit Theory Appl. 21(2): 191-195 (1993) - 1992
- [b1]Hubert Harrer:
Discrete time cellular neural networks. Technical University Munich, Germany, Shaker 1992, ISBN 978-3-86111-286-0, pp. 1-113 - [j2]Hubert Harrer, Josef A. Nossek:
Discrete-time cellular neural networks. Int. J. Circuit Theory Appl. 20(5): 453-467 (1992) - [j1]Hubert Harrer, Josef A. Nossek, Rudolf Stelzl:
An analog implementation of discrete-time cellular neural networks. IEEE Trans. Neural Networks 3(3): 466-476 (1992)
Coauthor Index
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