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2020 – today
- 2024
[j17]Zainab Aizaz
, Kavita Khare, Aizaz Tirmizi:
Approximate Row-Merging-Based Multipliers for Neural Network Acceleration on FPGAs. IEEE Embed. Syst. Lett. 16(2): 126-129 (2024)- 2023
- [j16]Zainab Aizaz, Kavita Khare:
ASMPEC: Approximate-Sum-Based Mapping of Partial Products With Error Correction for Softcore Multipliers on FPGAs. IEEE Trans. Circuits Syst. II Express Briefs 70(12): 4569-4573 (2023) - [c11]Zainab Aizaz, Kavita Khare, Mohd Anas Khan, Mahesh Kumar Singh, Vaithiyanathan Dhandapani:
A1RL: Approximate 1-Row-LUT-Based Low-Power Signed Multipliers for DSP and Machine Learning Applications on FPGAs. APCCAS 2023: 241-245 - [c10]Zainab Aizaz, Kavita Khare, Aizaz Tirmizi:
FASBM: FPGA-specific Approximate Sum-based Booth multipliers for energy efficient Hardware Acceleration of Image Processing and Machine Learning Applications. FCCM 2023: 210 - 2022
- [j15]Zainab Aizaz, Kavita Khare:
Energy efficient approximate booth multipliers using compact error compensation circuit for mitigation of truncation error. Int. J. Circuit Theory Appl. 50(6): 2252-2270 (2022) - [j14]Zainab Aizaz, Kavita Khare:
Area and Power Efficient Truncated Booth Multipliers Using Approximate Carry-Based Error Compensation. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 579-583 (2022) - 2021
- [j13]Divya Gautam, Kavita Khare, Bhavana P. Shrivastava:
A Novel Approach for Optimal Design of Sample Rate Conversion Filter Using Linear Optimization Technique. IEEE Access 9: 44436-44441 (2021)
2010 – 2019
- 2019
- [j12]Ajay Kumar Dadoria, Kavita Khare:
Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET Technology. Circuits Syst. Signal Process. 38(9): 4338-4356 (2019) - 2018
- [j11]Ajay Kumar Dadoria, Kavita Khare, Tarun Kumar Gupta, R. P. Singh:
New Leakage Reduction Techniques for FinFET Technology with Its Application. J. Circuits Syst. Comput. 27(7): 1850112:1-1850112:23 (2018) - 2016
- [j10]Supriya Aggarwal, Pramod Kumar Meher, Kavita Khare:
Concept, Design, and Implementation of Reconfigurable CORDIC. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1588-1592 (2016) - [c9]Ajay Kumar Dadoria, Kavita Khare, R. P. Singh:
Leakage Power Reduction Technique by using FinFET Technology. ICTCS 2016: 15:1-15:5 - [c8]Shailesh Dwivedi, Kavita Khare, Ajay Kumar Dadoria:
Low-Power High Speed 1-bit Full Adder Circuit Design. ICTCS 2016: 106:1-106:5 - 2013
- [j9]Tarun Kumar Gupta, Kavita Khare:
Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino Circuits. Circuits Syst. Signal Process. 32(6): 2707-2722 (2013) - [j8]Supriya Aggarwal, Kavita Khare:
CORDIC-based window implementation to minimise area and pipeline depth. IET Signal Process. 7(5): 427-435 (2013) - [j7]Supriya Aggarwal, Pramod Kumar Meher, Kavita Khare:
Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(2): 314-326 (2013) - [j6]Supriya Aggarwal, Kavita Khare:
Leading One Detection Hyperbolic CORDIC with Enhanced Range of Convergence. J. Signal Process. Syst. 70(1): 49-57 (2013) - [c7]Anita Jain, Kavita Khare:
3D CORDIC Algorithm Based Cartesian to Spherical Coordinate Converter. VDAT 2013: 337-344 - [c6]Supriya Aggarwal, Kavita Khare:
Efficient Window-Architecture Design Using Completely Scaling-Free CORDIC Pipeline. VLSI Design 2013: 60-65 - 2012
- [j5]Supriya Aggarwal, Kavita Khare:
Design Techniques Targeting Low-Area-Power-Delay Product in Hyperbolic CORDIC Algorithm. Comput. J. 55(5): 616-628 (2012) - [j4]Supriya Aggarwal, Kavita Khare:
Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency. Int. J. Reconfigurable Comput. 2012: 185784:1-185784:8 (2012) - [j3]Supriya Aggarwal, Pramod Kumar Meher, Kavita Khare:
Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1542-1546 (2012) - [j2]Sunanda Manke, Kavita Khare, S. D. Sapre:
FPGA Implementation of Cross Virtual Concatenation Transmitter/ Receiver for Data Transmission over Next Generation SDH Systems. J. Signal Process. Syst. 67(2): 105-116 (2012) - [c5]Supriya Aggarwal, Kavita Khare:
Hardware Efficient Architecture for Generating Sine/Cosine Waves. VLSI Design 2012: 57-61 - 2011
- [j1]Sunanda Manke, Kavita Khare, S. D. Sapre:
VCAT synchroniser - reduction of buffer size in VCAT enabled next generation SDH networks. Eur. Trans. Telecommun. 22(8): 500-514 (2011) - 2010
- [c4]J. Deshmukh, Kavita Khare:
Standby leakage reduction in nanoscale CMOS VLSI circuits. ICWET 2010: 911-914
2000 – 2009
- 2009
- [c3]Sunanda Manke, Kavita Khare, S. D. Sapre:
Differential Delay Compensator -- A New Approach to Reduce Buffer Size in VCAT Enabled Next Generation SDH Networks. ARTCom 2009: 244-248 - [c2]Vikas Gupta, Kavita Khare, R. P. Singh:
FPGA Design and Implementation Issues of Artificial Neural Network Based PID Controllers. ARTCom 2009: 860-862 - 2008
- [c1]Sunanda Manke, Kavita Khare, S. D. Sapre:
100Mbps Ethernet data transmission over SDH networks using Cross Virtual Concatenation. ICON 2008: 1-6
Coauthor Index
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