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ORCIDMudit Bhargava
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2020 – today
- 2023
[i5]Prithwish Basu Roy, Mudit Bhargava, Chia-Yun Chang, Ellen Hui, Nikhil Gupta, Ramesh Karri
, Hammond Pearce:
A survey of Digital Manufacturing Hardware and Software Trojans. CoRR abs/2301.10336 (2023)- 2021
- [c23]Rahul Mathur, Mudit Bhargava, Heath Perry, Alberto Cestero, Frank Frederick, Shawn Hung, Chien-Ju Chao, Daniel Smith, Daniel Fisher, Norman Robson, Xiaoqing Xu, Pranavi Chandupatla, Raguram Balachandran, Saurabh Sinha, Brian Cline, Jaydeep P. Kulkarni:
3D-Split SRAM: Enabling Generational Gains in Advanced CMOS. CICC 2021: 1-2 - [c22]Fernando García-Redondo, Pranay Prabhat, Mudit Bhargava:
A Fokker-Planck Solver to Model MTJ Stochasticity. ESSDERC 2021: 263-266 - [i4]Fernando García-Redondo, Pranay Prabhat, Mudit Bhargava, Cyrille Dray:
A Compact Model for Scalable MTJ Simulation. CoRR abs/2106.04976 (2021) - [i3]Fernando García-Redondo, Pranay Prabhat, Mudit Bhargava:
A Fokker-Planck Solver to Model MTJ Stochasticity. CoRR abs/2106.12304 (2021) - 2020
- [i2]Saurabh Sinha, Xiaoqing Xu, Mudit Bhargava, Shidhartha Das, Brian Cline, Greg Yeric:
Stack up your chips: Betting on 3D integration to augment Moore's Law scaling. CoRR abs/2005.10866 (2020)
2010 – 2019
- 2019
- [j1]Burak Erbagci, Nail Etkin Can Akkaya, Mudit Bhargava, Rachel Dondero, Ken Mai:
Secure hardware-entangled field programmable gate arrays. J. Parallel Distributed Comput. 131: 81-96 (2019) - [c21]Haitong Li, Mudit Bhargava, Paul N. Whatmough, H.-S. Philip Wong:
On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators. DAC 2019: 131 - [c20]Xiaoqing Xu, Mudit Bhargava, Steve Moore, Saurabh Sinha, Brian Cline:
Enhanced 3D Implementation of an Arm® Cortex®-A Microprocessor. ISLPED 2019: 1-6 - [c19]Cagla Cakir, Andy W. Chen, Y. K. Chong, Sriram Thyagarajan, Mark P. McCartney, Peixuan Tan, Yulin Shi, Mudit Bhargava:
A 4GHz 16nm SRAM Architecture with Low-Power Features for Heterogeneous Computing Platforms. VLSI Circuits 2019: 112- - 2015
- [c18]Mudit Bhargava, Kaship Sheikh, Ken Mai:
Robust true random number generator using hot-carrier injection balanced metastable sense amplifiers. HOST 2015: 7-13 - [c17]Burak Erbagci, Mudit Bhargava, Rachel Dondero, Ken Mai:
Deeply hardware-entangled reconfigurable logic and interconnect. ReConFig 2015: 1-8 - [i1]Mudit Bhargava, Ken Mai:
A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement. IACR Cryptol. ePrint Arch. 2015: 427 (2015) - 2014
- [c16]Mudit Bhargava, Ken Mai:
An efficient reliable PUF-based cryptographic key generator in 65nm CMOS. DATE 2014: 1-6 - [c15]Mudit Bhargava, Y. K. Chong, Vincent Schuppe, Bikas Maiti, Martin Kinkade, Hsin-Yu Chen, Andy W. Chen, Sanjay Mangal, Jacek Wiatrowski, Gerald Gouya, Abhishek Baradia, Sriram Thyagarajan, Gus Yeung:
Low VMIN 20nm embedded SRAM with multi-voltage wordline control based read and write assist techniques. VLSIC 2014: 1-2 - 2013
- [b1]Mudit Bhargava:
Reliable, Secure, Efficient Physical Unclonable Functions. Carnegie Mellon University, USA, 2013 - [c14]Mudit Bhargava, Pulkit Mehndiratta, Krishna Asawa:
Stylometric Analysis for Authorship Attribution on Twitter. BDA 2013: 37-47 - [c13]Mudit Bhargava, Ken Mai:
A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement. CHES 2013: 90-106 - [c12]Ben Niewenhuis, Ronald D. Blanton, Mudit Bhargava, Ken Mai:
SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states. ITC 2013: 1-8 - [c11]Jangwoo Kim, Hyunggyun Yang, Mark P. McCartney, Mudit Bhargava, Ken Mai, Babak Falsafi:
Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC. PRDC 2013: 98-107 - 2012
- [c10]Mudit Bhargava, Cagla Cakir, Ken Mai:
Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS. CICC 2012: 1-4 - [c9]Cagla Cakir, Mudit Bhargava, Ken Mai:
6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS. CICC 2012: 1-4 - [c8]Mudit Bhargava, Cagla Cakir, Ken Mai:
Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS. HOST 2012: 25-30 - 2011
- [c7]Yu Cai, Erich F. Haratsch, Mark P. McCartney, Mudit Bhargava, Ken Mai:
FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only). FPGA 2011: 284 - 2010
- [c6]Satyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun:
Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers. DAC 2010: 138-143 - [c5]Mudit Bhargava, Cagla Cakir, Ken Mai:
Attack Resistant Sense Amplifier based PUFs (SA-PUF) with Deterministic and Controllable Reliability of PUF Responses. HOST 2010: 106-111 - [c4]Craig Teegarden, Mudit Bhargava, Ken Mai:
Side-channel Attack Resistant ROM-based AES S-Box. HOST 2010: 124-129
2000 – 2009
- 2009
- [c3]Mudit Bhargava, Mark P. McCartney, Alexander Hoefler, Ken Mai:
Low-overhead, digital offset compensated, SRAM sense amplifiers. CICC 2009: 705-708 - [c2]Satyanand Nalam, Mudit Bhargava, Kyle Ringgenberg, Ken Mai, Benton H. Calhoun:
A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes. ICCD 2009: 523-528 - 2008
- [c1]Umut Arslan, Mark P. McCartney, Mudit Bhargava, Xin Li, Ken Mai, Lawrence T. Pileggi:
Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines. CICC 2008: 415-418
Coauthor Index
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