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ORCIDTeruhiko Yamada
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1990 – 1999
- 1999
[c7]Teruhiko Yamada, Toshinori Kotake, Hiroshi Takahashi, Koji Yamazaki:
Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset. Asian Test Symposium 1999: 269-274- 1998
- [j11]Teruhiko Yamada:
1997 Asian Test Symposium. IEEE Des. Test Comput. 15(1): 6- (1998) - [c6]Teruhiko Yamada, Tsuneto Hanashima, Yasuhiro Suemori, Masaaki Maezawa:
On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates. Asian Test Symposium 1998: 222-227 - 1997
- [c5]Koji Yamazaki, Teruhiko Yamada:
An approach to diagnose logical faults in partially observable sequential circuits. Asian Test Symposium 1997: 168-173 - 1996
- [c4]Teruhiko Yamada, Tsuyoshi Sasaki:
On Current Testing of Josephson Logic Circuits Using the 4JL Gate Family. Asian Test Symposium 1996: 189- - 1995
- [j10]Teruhiko Yamada:
Accelerating the Pace of R&D in Asia. IEEE Des. Test Comput. 12(3): 12-13 (1995) - [j9]Koji Yamazaki, Teruhiko Yamada:
A Single Bridging Fault Location Technique for CMOS Combinational Circuits. IEICE Trans. Inf. Syst. 78-D(7): 817-821 (1995) - [c3]Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey:
A simple technique for locating gate-level faults in combinational circuits. Asian Test Symposium 1995: 65-70 - 1992
- [j8]Teruhiko Yamada, Yoshiyuki Nakamura:
A method of diagnosing single stuck-at faults in combinational circuits. Syst. Comput. Jpn. 23(14): 35-44 (1992) - 1991
- [j7]Teruhiko Yamada, Koji Yamazaki:
Method of diagnosing single bridging faults in combinational circuit. Syst. Comput. Jpn. 22(9): 43-51 (1991) - [j6]Teruhiko Yamada, Shuji Hamada, Tatsuo Matsumoto, Toshihiko Takahashi, Takao Nakayama:
Method of diagnosing multiple stuck-at-faults in combinational circuits. Syst. Comput. Jpn. 22(11): 21-30 (1991) - 1990
- [j5]Teruhiko Yamada, Hiroshi Nakajima:
Pseudorandom pattern built-in self-test for embedded rams. Syst. Comput. Jpn. 21(12): 1-8 (1990)
1980 – 1989
- 1988
- [j4]Hideo Fujiwara, Yuzo Takamatsu, Takashi Nanya, Teruhiko Yamada, Hideo Tamamoto, Kiyoshi Furuya:
Test research in Japan. IEEE Des. Test 5(5): 60-79 (1988) - 1986
- [j3]Teruhiko Yamada:
Syndrome-testable design and syndrome computing method for large PLA's. Syst. Comput. Jpn. 17(4): 17-23 (1986) - 1985
- [c2]Yoshiyuki Koseki, Teruhiko Yamada:
PLAYER: a PLA design system for VLSI's. DAC 1985: 766-769 - 1984
- [j2]Teruhiko Yamada, Takashi Nanya:
Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults. IEEE Trans. Computers 33(8): 758-761 (1984) - 1983
- [j1]Teruhiko Yamada, Takashi Nanya:
Comments on "Detection Location of Input and Feedback Bridging Faults Among Input Output Lines". IEEE Trans. Computers 32(5): 511-512 (1983) - [c1]Teruhiko Yamada:
Syndrome-Testable Design of Programmable Logic Arrays. ITC 1983: 453-459
Coauthor Index
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