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ORCIDDavid J. Frank
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2020 – today
- 2024
[c9]Raphael Robertazzi, David J. Frank, Kevin Tien, John Timmerwilke, Peilin Song, Daniel J. Friedman:
Characterization of 14nm CMOS Technology At Cryogenic Temperatures Using Dense Addressable Arrays. VTS 2024: 1-7- 2023
- [c8]David J. Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Scott Lekuch, Ken Inoue, Devin Underwood, Dorothy Wisnieff, Chris Baks, John Timmerwilke, Peilin Song, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman:
Low power cryogenic RF ASICs for quantum computing. CICC 2023: 1-8 - 2022
- [j11]Sudipto Chakraborty
, David J. Frank, Kevin Tien, Pat Rosno, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Devin Underwood, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Dorothy Wisnieff, Christian W. Baks, Donald S. Bethune, John Timmerwilke, Thomas Fox, Peilin Song, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman:
A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology. IEEE J. Solid State Circuits 57(11): 3258-3273 (2022) - [c7]Kevin Tien, Ken Inoue, Scott Lekuch, David J. Frank, Sudipto Chakraborty, Pat Rosno, Thomas Fox, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Devin Underwood, Dorothy Wisnieff, Christian W. Baks, Donald Bethune, John Timmerwilke, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman:
A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation. DATE 2022: 13-16 - [c6]David J. Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Thomas Fox, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Devin Underwood, Dorothy Wisnieff, Christian W. Baks, Donald Bethune, John Timmerwilke, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman:
A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology. ISSCC 2022: 360-362
2010 – 2019
- 2016
- [c5]Ching Zhou, Yu-Shiang Lin, Pong-Fei Lu, Bruce M. Fleischer, David J. Frank, Leland Chang:
Synthesis design strategies for energy-efficient microprocessors. ICCD 2016: 103-108 - 2010
- [j10]Leland Chang, David J. Frank, Robert K. Montoye, Steven J. Koester, Brian L. Ji, Paul W. Coteus, Robert H. Dennard, Wilfried Haensch:
Practical Strategies for Power-Efficient Computing Technologies. Proc. IEEE 98(2): 215-236 (2010)
2000 – 2009
- 2006
- [j9]David J. Frank, Wilfried Haensch, Ghavam G. Shahidi, Omer H. Dokumaci:
Optimizing CMOS technology for maximum performance. IBM J. Res. Dev. 50(4-5): 419-432 (2006) - [j8]Kerry Bernstein, David J. Frank, Anne E. Gattiker, Wilfried Haensch, Brian L. Ji, Sani R. Nassif, Edward J. Nowak, Dale J. Pearson, Norman J. Rohrer:
High-performance CMOS variability in the 65-nm regime and beyond. IBM J. Res. Dev. 50(4-5): 433-450 (2006) - [j7]Anna W. Topol, Douglas C. La Tulipe Jr., Leathen Shi, David J. Frank, Kerry Bernstein, Steven E. Steen, Arvind Kumar, Gilbert U. Singco, Albert M. Young, Kathryn W. Guarini, Mei-Kei Ieong:
Three-dimensional integrated circuits. IBM J. Res. Dev. 50(4-5): 491-506 (2006) - [c4]David J. Frank, Ruchir Puri, Dorel Toma:
Design and CAD challenges in 45nm CMOS and beyond. ICCAD 2006: 329-333 - 2002
- [j6]David J. Frank:
Power-constrained CMOS scaling limits. IBM J. Res. Dev. 46(2-3): 235-344 (2002) - 2001
- [j5]David J. Frank, Robert H. Dennard, Edward J. Nowak, Paul M. Solomon, Yuan Taur, Hon-Sum Philip Wong:
Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE 89(3): 259-288 (2001)
1990 – 1999
- 1999
- [j4]Hon-Sum Philip Wong, David J. Frank, Paul M. Solomon, Clement H. J. Wann, Jefferey J. Welser:
Nanoscale CMOS. Proc. IEEE 87(4): 537-570 (1999) - 1997
- [j3]Yuan Taur, Douglas A. Buchanan, Wei Chen, David J. Frank, Khalid E. Ismail, Shih-Hsien Lo, George A. Sai-Halasz, Raman G. Viswanathan, Hsing-Jen C. Wann, Shalom J. Wind, Hon-Sum Philip Wong:
CMOS scaling into the nanometer regime. Proc. IEEE 85(4): 486-504 (1997) - [c3]David J. Frank, Paul M. Solomon, Scott K. Reynolds, John Shin:
Supply and threshold voltage optimization for low power design. ISLPED 1997: 317-322 - 1996
- [c2]David J. Frank:
Comparison of high speed voltage-scaled conventional and adiabatic circuits. ISLPED 1996: 377-380 - 1995
- [j2]Yuan Taur, Yuh-Jier Mii, David J. Frank, H.-S. Philip Wong, Douglas A. Buchanan, Shalom J. Wind, Stephen A. Rishton, Watson A. Sai-Halasz, Edward J. Nowak:
CMOS scaling into the 21st century: 0.1 µm and beyond. IBM J. Res. Dev. 39(1-2): 245-260 (1995) - [c1]David J. Frank, Paul M. Solomon:
Electroid-oriented adiabatic switching circuits. ISLPD 1995: 197-202
1980 – 1989
- 1988
- [j1]Randy R. Torrance, Steve P. Sadler, J. Pierre Lamoureux, Jean Lamarche, David J. Frank, Francois Leveille:
The design of a fully integrated graphics system. IEEE J. Solid State Circuits 23(2): 368-376 (1988)
Coauthor Index
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