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ORCIDHyungsoo Kim
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2020 – today
- 2023
[c12]Seokhyun Ryu, Sohyun Kim, Jaeyung Jun, Donguk Moon, Kyungsoo Lee, Jungmin Choi, Sunwoong Kim, Hyungsoo Kim, Luke Kim, Won Ha Choi, Moohyeon Nam, Dooyoung Hwang, Hongchan Roh, Young-Pyo Joo:
System Optimization of Data Analytics Platforms using Compute Express Link (CXL) Memory. BigComp 2023: 9-12- 2022
- [j4]Jihyo Kang
, Jaehyeok Yang, Kyunghoon Kim, Joo-Hyung Chae, Gang-Sik Lee, Sang-Yeon Byeon, Boram Kim, Dong-Hyun Kim, Youngtaek Kim, Yeongmuk Cho, Junghwan Ji, Sera Jeong, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Sunho Kim, Hae-Kang Jung, Jieun Jang, Sangkwon Lee, Hyungsoo Kim, Joo-Hwan Cho, Junhyun Chun, Seon-Yong Cha:
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation. IEEE J. Solid State Circuits 57(1): 212-223 (2022) - [c11]Miryeong Park, Kyungwoon Lee, Kanghee Seol, Minsoo Lee, Hyungsoo Kim:
Quality of Service Evaluation over a 496 km Quantum Key Distribution Network. SoftCOM 2022: 1-3 - 2021
- [j3]Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Gyutae Park, Jinil Chung, Kyeong-Min Kim, Hae-Kang Jung, Hyungsoo Kim, Junhyun Chun, Chulwoo Kim:
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. IEEE J. Solid State Circuits 56(6): 1886-1896 (2021) - [c10]Taesang Choi, Sangsik Yoon, Taeyeon Kim, Hyungsoo Kim:
Design and Implementation of Quantum Key Distribution Network Control and Management. ICTC 2021: 724-727 - [c9]Kyunghoon Kim, Joo-Hyung Chae, Jaehyeok Yang, Jihyo Kang, Gang-Sik Lee, Sang-Yeon Byeon, Youngtaek Kim, Boram Kim, Dong-Hyun Kim, Yeongmuk Cho, Kangmoo Choi, Hyeongyeol Park, Junghwan Ji, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Kyubong Kong, Sunho Kim, Sangkwon Lee, Junhyun Chun, Hyungsoo Kim, Seon-Yong Cha:
A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation. ISSCC 2021: 344-346
2010 – 2019
- 2017
- [c8]Woojun Choi, Taewoong Kim, Jongjoo Shim, Hyungsoo Kim, Gunhee Han, Youngcheol Chae:
23.8 A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4. ISSCC 2017: 402-403 - 2015
- [c7]Sumin Choi, Heegon Kim, Daniel H. Jung, Jonghoon J. Kim, Jaemin Lim, Hyunsuk Lee, Kyungjun Cho, Joungho Kim, Hyungsoo Kim, Yong-Ju Kim, Yunsaing Kim:
Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC. 3DIC 2015: TS8.25.1-TS8.25.5 - [c6]Hae-Kang Jung, Jaemo Yang, Jeonghun Lee, Hyeongjun Ko, Hyuk Lee, Taeksang Song, Jongjoo Shim, Sangkwon Lee, Keunsoo Song, Dongkyun Kim, Hyungsoo Kim, Yunsaing Kim:
A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications. VLSIC 2015: 184- - 2012
- [c5]Sungbong Chang, Hyungsoo Kim, Byungdeok Chung, Hyunchul Jung:
Energy/carbon management network for IT equipments. APNOMS 2012: 1-5 - [c4]Kibong Koo, Sunghwa Ok, Yonggu Kang, Seungbong Kim, Choungki Song, Hyeyoung Lee, Hyungsoo Kim, Yongmi Kim, Jeonghun Lee, Seunghan Oak, Yosep Lee, Jungyu Lee, Joongho Lee, Hyungyu Lee, Jaemin Jang, Jongho Jung, Byeongchan Choi, Yong-Ju Kim, Youngdo Hur, Yunsaing Kim, Byong-Tae Chung, Yongtak Kim:
A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture. ISSCC 2012: 40-41 - [c3]Kyu-Nam Lim, Woong-Ju Jang, Hyung-Sik Won, Kang-Yeol Lee, Hyungsoo Kim, Dong-Whee Kim, Mi-Hyun Cho, Seung-Lo Kim, Jong-Ho Kang, Keun-Woo Park, Byung-Tae Jeong:
A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture. ISSCC 2012: 42-44
2000 – 2009
- 2009
- [c2]Hyungsoo Kim, Hyounkuk Kim, Namshik Kim, Hyuncheol Park, Seok Seo, Jin-Kyu Choi:
Efficient transmit antenna selection for correlated MIMO channels. WCNC 2009: 27-31 - 2008
- [j2]Hyunjeong Park, Hyungsoo Kim, Junso Pak, Changwook Yoon, Kyoungchoul Koo, Joungho Kim:
Co-modeling, Experimental Verification, and Analysis of Chip-Package Hierarchical Power Distribution Network. IEICE Trans. Electron. 91-C(4): 595-606 (2008) - 2006
- [j1]Daehyun Chung, Chunghyun Ryu, Hyungsoo Kim, Choonheung Lee, Jinhan Kim, Kicheol Bae, Jiheon Yu, Hoi-Jun Yoo, Joungho Kim:
Chip-package hybrid clock distribution network and DLL for low jitter clock delivery. IEEE J. Solid State Circuits 41(1): 274-286 (2006) - 2005
- [c1]Joungho Kim, Junso Pak, Jongbae Park, Hyungsoo Kim:
Noise generation, coupling, isolation, and EM radiation in high-speed package and PCB. ISCAS (6) 2005: 5766-5769
Coauthor Index
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