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2020 – today
- 2023
[j25]Hritom Das
, Ali Ahmad Haidous, Scott C. Smith, Na Gong:
Approximate Memory for Low-Power Video Applications. IEEE Access 11: 57735-57744 (2023)- [j24]Danylo Khodosevych, Alexander C. Bodoh, Ashiq A. Sakib, Scott C. Smith:
Combining Relaxation With NCL_X for Enhanced Optimization of Asynchronous Null Convention Logic Circuits. IEEE Access 11: 104688-104699 (2023) - 2022
- [j23]Brett Sparkman, Scott C. Smith, Jia Di:
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism. J. Electron. Test. 38(3): 321-334 (2022) - [j22]Kushal K. Ponugoti, Sudarshan K. Srinivasan, Scott C. Smith, Nimish Mathure:
Illegal Trojan design and detection in asynchronous NULL Convention Logic and Sleep Convention Logic circuits. IET Comput. Digit. Tech. 16(5-6): 172-182 (2022) - 2021
- [j21]Jingyan Fu, Zhiheng Liao, Jianqing Liu, Scott C. Smith, Jinhui Wang:
Memristor-Based Variation-Enabled Differentially Private Learning Systems for Edge Computing in IoT. IEEE Internet Things J. 8(12): 9672-9682 (2021) - [j20]Hritom Das, Ali Ahmad Haidous, Scott C. Smith, Na Gong:
Flexible Low-Cost Power-Efficient Video Memory With ECC-Adaptation. IEEE Trans. Very Large Scale Integr. Syst. 29(10): 1693-1706 (2021) - [c37]BoHyun Ahn, Taesic Kim, Scott C. Smith, Young-Woo Youn, Myung-Hyo Ryu:
Security Threat Modeling for Power Transformers in Cyber-Physical Environments. ISGT 2021: 1-5 - 2020
- [j19]Nauman Jalil, Scott C. Smith, Roger Green:
Performance optimization of rotation-tolerant Viola-Jones-based blackbird detection. J. Real Time Image Process. 17(3): 471-478 (2020) - [j18]Sahibzada Muhammad Ali, Muhammad Jawad, Muhammad Usman Shahid Khan, Kashif Bilal, Jacob Glower, Scott C. Smith, Samee U. Khan, Keqin Li, Albert Y. Zomaya:
An Ancillary Services Model for Data Centers and Power Systems. IEEE Trans. Cloud Comput. 8(4): 1176-1188 (2020) - [c36]Kushal K. Ponugoti, Sudarshan K. Srinivasan, Scott C. Smith:
Hardware Trojan Design and Detection in Asynchronous NCL Circuits. ICECS 2020: 1-4 - [c35]Ashiq A. Sakib, Scott C. Smith:
Implementation of Static NCL Threshold Gates Using Emerging CNTFET Technology. ICECS 2020: 1-4 - [c34]Son N. Le, Sudarshan K. Srinivasan, Scott C. Smith:
Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits. MWSCAS 2020: 21-24 - [c33]Son N. Le, Sudarshan K. Srinivasan, Scott C. Smith:
Formal Verification of Completion-Completeness for NCL Circuits. MWSCAS 2020: 25-28 - [c32]Nauman Jalil, Scott C. Smith:
Further Speedup of a Large Word-Width High-Speed Asynchronous Multiply and Accumulate Unit. MWSCAS 2020: 33-36 - [c31]Ashiq A. Sakib, Abir A. Akib, Scott C. Smith:
Implementation of FinFET Based Static NCL Threshold Gates: An Analysis of Design Choice. MWSCAS 2020: 37-40 - [c30]Brett Sparkman, Scott C. Smith, Jia Di:
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits. VTS 2020: 1-6
2010 – 2019
- 2019
- [j17]Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan:
Formal Modeling and Verification of PCHB Asynchronous Circuits. IEEE Trans. Very Large Scale Integr. Syst. 27(12): 2911-2924 (2019) - [c29]Mousam Hossain, Ashiq A. Sakib, Sudarshan K. Srinivasan, Scott C. Smith:
An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits. ISCAS 2019: 1-5 - 2018
- [c28]Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan:
An Equivalence Verification Methodology for Combinational Asynchronous PCHB Circuits. MWSCAS 2018: 767-770 - 2017
- [c27]Nasim Soufizadeh-Balaneji, Scott C. Smith:
Analysis and design of CMOS resettable C-elements. MWSCAS 2017: 104-107 - [c26]Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan:
Formal modeling and verification for pre-charge half buffer gates and circuits. MWSCAS 2017: 519-522 - [c25]Paul Rogers, Rajesh Kavasseri, Scott C. Smith:
An FPGA-in-the-loop approach for HDL motor controller verification. ReConFig 2017: 1-6 - 2016
- [j16]Farhad Alibeygi Parsan, Scott C. Smith, Waleed K. Al-Assadi:
Design for Testability of Sleep Convention Logic. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 743-753 (2016) - [c24]Paul Rogers, Rajesh Kavasseri, Scott C. Smith:
An FPGA-based design for joint control and monitoring of permanent magnet synchronous motors. ReConFig 2016: 1-6 - 2014
- [j15]Farhad Alibeygi Parsan, Waleed K. Al-Assadi, Scott C. Smith:
Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 99-112 (2014) - [c23]Vidura Wijayasekara, Sudarshan K. Srinivasan, Scott C. Smith:
Equivalence verification for NULL Convention Logic (NCL) circuits. ICCD 2014: 195-201 - [c22]Farhad Alibeygi Parsan, J. Zhao, Scott C. Smith:
SCL design of a pipelined 8051 ALU. MWSCAS 2014: 885-888 - 2013
- [j14]Michael Hinds, Brett Sparkman, Jia Di, Scott C. Smith:
An Asynchronous Advanced Encryption Standard Core Design for Energy Efficiency. J. Low Power Electron. 9(2): 175-188 (2013) - [j13]Washington Cilio, Michael Linder, Chris Porter, Jia Di, Dale R. Thompson, Scott C. Smith:
Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic. Microelectron. J. 44(3): 258-269 (2013) - [c21]Parviz Palangpour, Scott C. Smith:
Sleep Convention Logic using partially slept function blocks. MWSCAS 2013: 17-20 - [c20]Pragadesh Varadharajan, Waleed K. Al-Assadi, Shabab F. Alam, Scott C. Smith:
Quantum-dot cellular automaton of asynchronous Null Convention Logic multiplier design. MWSCAS 2013: 813-816 - 2012
- [c19]Robert B. Reese, Scott C. Smith, Mitchell A. Thornton:
Uncle - An RTL Approach to Asynchronous Design. ASYNC 2012: 65-72 - [c18]Farhad Alibeygi Parsan, Scott C. Smith:
CMOS implementation comparison of NCL gates. MWSCAS 2012: 394-397 - [c17]Farhad Alibeygi Parsan, Scott C. Smith:
CMOS implementation of static threshold gates with hysteresis: A new approach. VLSI-SoC 2012: 41-45 - [c16]Farhad Alibeygi Parsan, Scott C. Smith:
CMOS Implementation of Threshold Gates with Hysteresis. VLSI-SoC (Selected Papers) 2012: 196-216 - 2010
- [j12]Scott C. Smith, Waleed K. Al-Assadi, Jia Di:
Integrating Asynchronous Digital Design Into the Computer Engineering Curriculum. IEEE Trans. Educ. 53(3): 349-357 (2010) - [c15]Scott C. Smith, David Roclin, Jia Di:
Delay-Insensitive Cell Matrix. CDES 2010: 67-73
2000 – 2009
- 2009
- [b1]Scott C. Smith, Jia Di:
Designing Asynchronous Circuits using NULL Convention Logic (NCL). Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers 2009, ISBN 978-3-031-79799-6 - [c14]Brent Hollosi, Tao Zhang, Ravi Sankar Parameswaran Nair, Yuan Xie, Jia Di, Scott C. Smith:
Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs. 3DIC 2009: 1-5 - [c13]Ravi Sankar Parameswaran Nair, Scott C. Smith, Jia Di:
Delay-Insensitive Ternary Logic. CDES 2009: 3-0 - [c12]Parviz Palangpour, Ganesh K. Venayagamoorthy, Scott C. Smith:
Particle Swarm Optimization: A Hardware Implementation. CDES 2009: 134-139 - [c11]Jingxian Wu, Scott C. Smith:
Integrated software-hardware design for ultra-low power infrastructure monitoring. ITSC 2009: 1-8 - 2008
- [j11]Andrew Bailey, Ahmad Al Zahrani, Guoyuan Fu, Jia Di, Scott C. Smith:
Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power. J. Low Power Electron. 4(3): 337-348 (2008) - 2007
- [j10]Ganesh K. Venayagamoorthy, Scott C. Smith, Gaurav Singhal:
Particle swarm-based optimal partitioning algorithm for combinational CMOS circuits. Eng. Appl. Artif. Intell. 20(2): 177-184 (2007) - [j9]Venkat Satagopan, Bonita Bhaskaran, Anshul Singh, Scott C. Smith:
Automated energy calculation and estimation for delay-insensitive digital circuits. Microelectron. J. 38(10-11): 1095-1107 (2007) - [j8]Scott C. Smith:
Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 15(6): 672-683 (2007) - [j7]Venkat Satagopan, Bonita Bhaskaran, Waleed K. Al-Assadi, Scott C. Smith, Sindhu Kakarla:
DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 15(10): 1155-1159 (2007) - [c10]Scott C. Smith:
Design of a logic element for implementing an asynchronous FPGA. FPGA 2007: 13-22 - 2006
- [j6]Scott C. Smith:
Speedup of NULL convention digital circuits using NULL cycle reduction. J. Syst. Archit. 52(7): 411-422 (2006) - 2005
- [j5]Scott C. Smith:
Development of a large word-width high-speed asynchronous multiply and accumulate unit. Integr. 39(1): 12-28 (2005) - [c9]Bonita Bhaskaran, Venkat Satagopan, Scott C. Smith:
High-Speed Energy Estimation for Delay-Insensitive Circuits. CDES 2005: 35-41 - [c8]Bonita Bhaskaran, Venkat Satagopan, Waleed K. Al-Assadi, Scott C. Smith:
Implementation of Design For Test for Asynchronous NCL Designs. CDES 2005: 78-84 - [c7]Anshul Singh, Scott C. Smith:
Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation. CDES 2005: 115-121 - 2004
- [j4]Scott C. Smith, Ronald F. DeMara, Jiann-Shiun Yuan, Dennis Ferguson, D. Lamb:
Optimization of NULL convention self-timed circuits. Integr. 37(3): 135-165 (2004) - [c6]Scott C. Smith:
Designing NULL Convention Combinational Circuits to Fully Utilize Gate-Level Pipelining for Maximum Throughput. ESA/VLSI 2004: 407-412 - [c5]Scott C. Smith:
Design of a NULL Convention Self-Timed Divider. ESA/VLSI 2004: 447-453 - 2003
- [j3]Satish K. Bandapati, Scott C. Smith, Minsu Choi:
Design and Characterization of Null Convention Self-Timed Multipliers. IEEE Des. Test Comput. 20(6): 26-36 (2003) - [c4]Scott C. Smith, James Fisher:
On generating random systems: a gramian approach. ACC 2003: 2743-2748 - [c3]Scott C. Smith:
Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion Strategy. VLSI 2003: 143-149 - [c2]Satish K. Bandapati, Scott C. Smith:
Design and Characterization of NULL Convention Arithmetic Logic Units. VLSI 2003: 178-184 - 2002
- [j2]Scott C. Smith, Ronald F. DeMara, Jiann-Shiun Yuan, M. Hagedorn, Dennis Ferguson:
NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation. J. Syst. Archit. 47(12): 977-998 (2002) - [c1]Scott C. Smith:
Speedup of Self-Timed Digital Systems Using Early Completion. ISVLSI 2002: 107-116 - 2001
- [j1]Scott C. Smith, Ronald F. DeMara, Jiann-Shiun Yuan, M. Hagedorn, Dennis Ferguson:
Delay-insensitive gate-level pipelining. Integr. 30(2): 103-131 (2001)
Coauthor Index
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