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ORCIDAndrea Gerosa
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2020 – today
- 2024
[c42]Andrea Gerosa
:
Work in Progress: Systems Thinking as a Foundation for Sustainability Awareness and Ethical Use of Technologies. EDUCON 2024: 1-3- [c41]Andrea Pasin, Lorenza Da Re, Andrea Gerosa, Lidia Pezzuoli, Silvia Preciso, Nicola Ferro:
PNRRorienta: A Web Application for Managing Schools, Courses, and Students Involved in the PNRR Orientation Initiative. SEBD 2024: 468-476 - 2023
- [j16]Lorenza Da Re, Roberta Bonelli, Andrea Gerosa:
Formative Tutoring: A Program for the Empowerment of Engineering Students. IEEE Trans. Educ. 66(2): 163-173 (2023) - 2022
- [c40]Francesca Chiocchetta, Carlo De Santi, Fabiana Rampazzo, Kalparupa Mukherjee, Jan Grünenpütt, Daniel Sommer, Hervé Blanck, Benoit Lambert, Andrea Gerosa, Gaudenzio Meneghesso, Enrico Zanoni, Matteo Meneghini:
GaN RF HEMT Reliability: Impact of Device Processing on I-V Curve Stability and Current Collapse. IRPS 2022: 11
2010 – 2019
- 2019
- [c39]Alberto Gatti, Giorgio Spiazzi, Andrea Gerosa, Andrea Neviani, Andrea Bevilacqua:
A 130-nm CMOS Dual Input-Polarity DC-DC Converter for Low-Power Applications. ESSCIRC 2019: 211-214 - [c38]Andrea Gerosa, Andrea Bevilacqua, Giorgio Spiazzi:
A Multi-Phase Self-Reconfigurable Switched-Capacitor DC-DC Step-Up Converter Integrated in CMOS Technology. ISCAS 2019: 1-5 - 2016
- [c37]Alberto Celin, Andrea Gerosa:
A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior. ISCAS 2016: 702-705 - 2015
- [c36]Alberto Celin, Andrea Gerosa:
Optimal DWA design in scaled CMOS technologies for mismatch cancellation in multibit ΣΔ ADCs. ISCAS 2015: 1454-1457 - 2012
- [j15]Matteo Bassi, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani:
Integrated SFCW Transceivers for UWB Breast Cancer Imaging: Architectures and Circuit Constraints. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(6): 1228-1241 (2012) - [c35]Andrea Neviani, Andrea Bevilacqua, Andrea Gerosa, Daniele Vogrig:
Low-power ultra-Wide-Band Impulse Radio transceivers for short range communications. ICICDT 2012: 1-4 - 2011
- [j14]Silvia Soldà, Michele Caruso, Andrea Bevilacqua, Andrea Gerosa, Daniele Vogrig, Andrea Neviani:
A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13 μm CMOS. IEEE J. Solid State Circuits 46(7): 1636-1647 (2011) - [c34]Matteo Bassi, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani:
Integrated transceivers for UWB breast cancer imaging: Architecture and circuit constraints. ISCAS 2011: 2087-2090 - 2010
- [j13]Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani:
A 0.06 mm 2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS. IEEE J. Solid State Circuits 45(7): 1295-1304 (2010) - [c33]Andrea Bevilacqua, Leonardo Lorenzon, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani:
A 4.1 to 5.1 GHz 430 μA injection-locked frequency divider by 7 in 65 nm CMOS. ESSCIRC 2010: 150-153 - [c32]Silvia Soldà, Michele Caruso, Andrea Bevilacqua, Andrea Gerosa, Daniele Vogrig, Andrea Neviani:
A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request. ESSCIRC 2010: 498-501 - [c31]Silvia Soldà, Michele Caruso, Daniele Vogrig, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani:
Low-power UWB transmitter using a combined mixer and power amplifier. ISCAS 2010: 333-336 - [c30]Andrea Gerosa, Silvia Soldà, Andrea Bevilacqua, Daniele Vogrig, Andrea Neviani:
A digitally programmable ring oscillator in the UWB range. ISCAS 2010: 1101-1104 - [c29]Stefano Dal Toso, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani:
A thorough analysis of the tank quality factor in LC oscillators with switched capacitor banks. ISCAS 2010: 1903-1906
2000 – 2009
- 2009
- [j12]Alessio Vallese, Andrea Bevilacqua, Christoph Sandner, Marc Tiebout, Andrea Gerosa, Andrea Neviani:
Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems. IEEE J. Solid State Circuits 44(2): 331-343 (2009) - [j11]Andrea Gerosa, Silvia Soldà, Andrea Bevilacqua, Daniele Vogrig, Andrea Neviani:
An Energy-Detector for Noncoherent Impulse-Radio UWB Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(5): 1030-1040 (2009) - [c28]Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Nicola Da Dalt, Andrea Gerosa, Andrea Neviani:
A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS. ESSCIRC 2009: 444-447 - 2008
- [j10]Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Stefano Marsili, Christoph Sandner, Andrea Gerosa, Andrea Neviani:
UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking. IEEE J. Solid State Circuits 43(12): 2844-2852 (2008) - [c27]Silvia Soldà, Daniele Vogrig, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani:
Analog decoding of trellis coded modulation for multi-level flash memories. ISCAS 2008: 744-747 - [c26]Andrea Bevilacqua, Matteo Camponeschi, Marc Tiebout, Andrea Gerosa, Andrea Neviani:
Design of broadband inductorless LNAs in ultra-scaled CMOS technologies. ISCAS 2008: 1300-1303 - [c25]Andrea Gerosa, Maurizio Dalla Costa, Andrea Bevilacqua, Daniele Vogrig, Andrea Neviani:
An energy-detector for non-coherent impulse-radio UWB receivers. ISCAS 2008: 2705-2708 - [c24]Stefano Dal Toso, Andrea Bevilacqua, Marc Tiebout, Stefano Marsili, Christoph Sandner, Andrea Gerosa, Andrea Neviani:
UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking. ISSCC 2008: 124-125 - 2007
- [j9]Andrea Bevilacqua, Federico P. Pavan, Christoph Sandner, Andrea Gerosa, Andrea Neviani:
Transformer-Based Dual-Mode Voltage-Controlled Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 54-II(4): 293-297 (2007) - [j8]Andrea Bevilacqua, Andrea Maniero, Andrea Gerosa, Andrea Neviani:
An Integrated Solution for Suppressing WLAN Signals in UWB Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(8): 1617-1625 (2007) - [c23]Alessio Vallese, Andrea Bevilacqua, Christoph Sandner, Marc Tiebout, Andrea Gerosa, Andrea Neviani:
An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 μm CMOS. ESSCIRC 2007: 139-142 - [c22]Andrea Gerosa, M. Soldan, Alessandro Bevilacqua, Andrea Neviani:
A 0.18-µm CMOS Squarer Circuit for a Non-Coherent UWB Receiver. ISCAS 2007: 421-424 - [c21]Andrea Bevilacqua, Christoph Sandner, Andrea Gerosa, Andrea Neviani:
Quadrature VCOs Based on Coupled PLLs. ISCAS 2007: 2140-2143 - [c20]Andrea Bevilacqua, Alessio Vallese, Christoph Sandner, Marc Tiebout, Andrea Gerosa, Andrea Neviani:
A 0.13μm CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers. ISSCC 2007: 420-612 - 2006
- [j7]Andrea Gerosa, Andrea Xotta, Andrea Bevilacqua, Andrea Neviani:
An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling Sigma Delta Modulator and a Flash Converter. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(10): 2109-2124 (2006) - [j6]Alexandre Graell i Amat, Sergio Benedetto, Guido Montorsi, Daniele Vogrig, Andrea Neviani, Andrea Gerosa:
Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code. IEEE Trans. Commun. 54(6): 1143 (2006) - [j5]Alexandre Graell i Amat, Sergio Benedetto, Guido Montorsi, Daniele Vogrig, Andrea Neviani, Andrea Gerosa:
Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code. IEEE Trans. Commun. 54(11): 1973-1982 (2006) - [c19]Alexandre Graell i Amat, Daniele Vogrig, Sergio Benedetto, Guido Montorsi, Andrea Neviani, Andrea Gerosa:
Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code. GLOBECOM 2006 - [c18]Andrea Maniero, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani:
A low-voltage III-order log-domain filter in standard CMOS technology with tunable frequency. ICECS 2006: 90-93 - [c17]Andrea Bevilacqua, Andrea Maniero, Andrea Gerosa, Andrea Neviani:
A 0.35 μm SiGe Low-Noise Amplifier for UWB, Receivers with Integrated Interferer Rejection. ICECS 2006: 1015-1018 - [c16]Andrea Gerosa, Andrea Bevilacqua, Andrea Neviani, Andrea Xotta:
An optimal architecture for a multimode ADC, based on the cascade of a Sigma Delta modulator and a flash converter. ISCAS 2006 - 2005
- [j4]Daniele Vogrig, Andrea Gerosa, Andrea Neviani, Alexandre Graell i Amat, Guido Montorsi, Sergio Benedetto:
A 0.35-μm CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code. IEEE J. Solid State Circuits 40(3): 753-762 (2005) - [j3]Andrea Gerosa, Andrea Neviani:
A 1.8-μW sigma-delta modulator for 8-bit digitization of cardiac signals in implantable pacemakers operating down to 1.8 V. IEEE Trans. Circuits Syst. II Express Briefs 52-II(2): 71-76 (2005) - [c15]Alexandre Graell i Amat, Sergio Benedetto, Guido Montorsi, Daniele Vogrig, Andrea Neviani, Andrea Gerosa:
An analog turbo decoder for the rate-1/3, 40 bit, UMTS turbo code. ICC 2005: 663-667 - [c14]Andrea Xotta, Andrea Gerosa, Andrea Neviani:
A multi-mode Sigma-Delta analog-to-digital converter for GSM, UMTS and WLAN. ISCAS (3) 2005: 2551-2554 - 2004
- [j2]Andrea Gerosa, Andrea Maniero, Andrea Neviani:
A fully integrated two-channel A/D interface for the acquisition of cardiac signals in implantable pacemakers. IEEE J. Solid State Circuits 39(7): 1083-1093 (2004) - [j1]Andrea Gerosa, Andrea Maniero, Andrea Neviani:
A fully integrated dual-channel log-domain programmable preamplifier and filter for an implantable cardiac pacemaker. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(10): 1916-1925 (2004) - [c13]Andrea Gerosa, Andrea Neviani:
A low-power decimation filter for a sigma-delta converter based on a power-optimized sinc filter. ISCAS (2) 2004: 245-248 - [c12]Alexandre Graell i Amat, Guido Montorsi, Sergio Benedetto, Daniele Vogrig, Andrea Neviani, Andrea Gerosa:
An analog turbo decoder for the UMTS standard. ISIT 2004: 296 - 2003
- [c11]Andrea Gerosa, Andrea Maniero, Andrea Neviani:
A fully-integrated two-channel A/D interface for the acquisition of cardiac signals in implantable pacemakers. ESSCIRC 2003: 157-160 - [c10]Andrea Gerosa, Andrea Neviani:
A very low-power 8-bit Sigma-Delta converter in a 0.8µm CMOS technology for the sensing chain of a cardiac pacemaker, operating down to 1.8 V. ISCAS (5) 2003: 49-52 - [c9]Andrea Maniero, Andrea Gerosa, Andrea Neviani:
Performance optimization in micro-power, low-voltage log-domain filters in pure CMOS technology. ISCAS (1) 2003: 565-568 - [c8]Matteo Perenzoni, Andrea Gerosa, Andrea Neviani:
Analog CMOS implementation of Gallager's iterative decoding algorithm applied to a block turbo code. ISCAS (5) 2003: 813-816 - 2002
- [c7]Andrea Xotta, Daniele Vogrig, Andrea Gerosa, Andrea Neviani, Alexandre Graell i Amat, Guido Montorsi, Melchiorre Bruccoleri, Giorgio Betti:
An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels. ISCAS (5) 2002: 69-72 - 2001
- [c6]Andrea Gerosa:
A ready-to-use design procedure for operational transconductance amplifiers that minimizes power consumption. ICECS 2001: 949-952 - [c5]Andrea Gerosa, Andrea Neviani, Andrea Xotta, Gian Antonio Mian:
A novel architecture to reduce complexity in hard disk read channel based on fractionally spaced equalization. ICECS 2001: 1099-1102 - [c4]Andrea Gerosa, Arianna Novo, Andrea Mengalli, Andrea Neviani:
A micro-power low noise log-domain amplifier for the sensing chain of a cardiac pacemaker. ISCAS (1) 2001: 296-299 - 2000
- [c3]Andrea Gerosa, Arianna Novo, Andrea Neviani:
Low-power sensing and digitization of cardiac signals based on sigma-delta conversion (poster session). ISLPED 2000: 216-218
1990 – 1999
- 1999
- [c2]Andrea Gerosa, Gian Antonio Mian:
A low complexity EPR-IV equalizer for hard disk read channels. ICECS 1999: 1069-1072 - 1996
- [c1]G. M. Cortdazzo, E. Malavasi, Andrea Gerosa, Andrea Neviani, A. Basckirotto:
A new structure for video-rate 2D SC FIR filters. EUSIPCO 1996: 1-4
Coauthor Index
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