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ORCIDElisenda Roca
Elisenda Roca Moreno
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- affiliation: Institute of Microelectronics of Seville, (IMSE-CNM-CSIC), Spain
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2020 – today
- 2023
[c63]Javier Martín-Martínez, Javier Diaz-Fortuny
, Pablo Saraza-Canflanca, Rosana Rodríguez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Montserrat Nafría:
Challenges and solutions to the defect-centric modeling and circuit simulation of time-dependent variability. IRPS 2023: 1-9- [c62]Victor M. van Santen, Jose M. Gata-Romero, Juan Núñez, Rafael Castro-López, Elisenda Roca, Hussam Amrouch:
Characterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths. IRPS 2023: 1-6 - [c61]Eros Camacho-Ruiz, F. J. Rubio-Barbero, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
Design considerations for a CMOS 65-nm RTN-based PUF. SMACD 2023: 1-4 - [c60]Francisco V. Fernández, Elisenda Roca, Pablo Saraza-Canflanca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Rafael Castro-López:
Strategies for parameter extraction of the time constant distribution of time-dependent variability models for nanometer-scale devices. SMACD 2023: 1-4 - [c59]Jose M. Gata-Romero, Elisenda Roca, Juan Núñez, Rafael Castro-López, Francisco V. Fernández:
Reliability evaluation of IC Ring Oscillator PUFs. SMACD 2023: 1-4 - [c58]Jose M. Gata-Romero, Andrés Santana-Andreo, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández:
A Test Module for Aging Characterization of Digital Circuits. SMACD 2023: 1-4 - [c57]F. J. Rubio-Barbero, Eros Camacho-Ruiz, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
A Peak Detect & Hold circuit to measure and exploit RTN in a 65-nm CMOS PUF. SMACD 2023: 1-4 - [c56]Andrés Santana-Andreo, Pablo Saraza-Canflanca, Héctor Carrasco-Lopez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
A detailed, cell-by-cell look into the effects of aging on an SRAM PUF using a specialized test array. SMACD 2023: 1-4 - 2022
- [j26]Andrés Santana-Andreo, Pablo Saraza-Canflanca, Héctor Carrasco-Lopez, Piedad Brox, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
A DRV-based bit selection method for SRAM PUF key generation and its impact on ECCs. Integr. 85: 1-9 (2022) - [j25]Pablo Saraza-Canflanca, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández:
On the Impact of the Biasing History on the Characterization of Random Telegraph Noise. IEEE Trans. Instrum. Meas. 71: 1-10 (2022) - [c55]Pablo Saraza-Canflanca, Héctor Carrasco-Lopez, Andrés Santana-Andreo, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies. IRPS 2022: 3-1 - [c54]Eros Camacho-Ruiz, Rafael Castro-López, Elisenda Roca, Piedad Brox, Francisco V. Fernández:
A novel Physical Unclonable Function using RTN. ISCAS 2022: 160-164 - [c53]Eros Camacho-Ruiz, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
High-level design of a novel PUF based on RTN. SMACD 2022: 1-4 - [c52]Eros Camacho-Ruiz, Andrés Santana-Andreo, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
On the use of an RTN simulator to explore the quality trade-offs of a novel RTN-based PUF. SMACD 2022: 1-4 - [c51]Fábio Passos, Nuno C. Lourenço, Ricardo Martins, Elisenda Roca, Rafael Castro-López, Nuno Horta, Francisco V. Fernández:
Machine Learning Approaches for Transformer Modeling. SMACD 2022: 1-4 - [c50]Andrés Santana-Andreo, Pablo Martín-Lloret, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández:
Characterization and analysis of BTI and HCI effects in CMOS current mirrors. SMACD 2022: 1-4 - [c49]Andrés Santana-Andreo, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández:
Impact of BTI and HCI on the reliability of a Majority Voter. SMACD 2022: 1-4 - [c48]Pablo Saraza-Canflanca, Javier Martín-Martínez, Elisenda Roca, Rafael Castro-López, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández:
A systematic approach to RTN parameter fitting based on the Maximum Current Fluctuation. SMACD 2022: 1-4 - 2021
- [j24]António Canelas, Fábio Passos, Nuno Lourenço, Ricardo Martins, Elisenda Roca, Rafael Castro-López, Nuno Horta, Francisco V. Fernández:
Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs. IEEE Access 9: 124152-124164 (2021) - 2020
- [j23]Fábio Passos, Elisenda Roca, Ricardo Martins, Nuno Lourenço, Saiyd Ahyoune, Javier J. Sieiro, Rafael Castro-López, Nuno Horta, Francisco V. Fernández:
Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology. IEEE Access 8: 51601-51609 (2020) - [j22]Pablo Saraza-Canflanca, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández:
A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level. Integr. 72: 13-20 (2020) - [j21]Fábio Passos, Elisenda Roca, Javier J. Sieiro, Rafaella Fiorelli, Rafael Castro-López, José María López-Villegas, Francisco V. Fernández:
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 560-571 (2020) - [j20]Fábio Passos, Miguel Chanca, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández:
Synthesis of mm-Wave Wideband Receivers in 28-nm CMOS Technology for Automotive Radar Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4375-4384 (2020) - [j19]Javier Diaz-Fortuny, Pablo Saraza-Canflanca, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Francisco V. Fernández, Montserrat Nafría:
Flexible Setup for the Measurement of CMOS Time-Dependent Variability With Array-Based Integrated Circuits. IEEE Trans. Instrum. Meas. 69(3): 853-864 (2020) - [c47]Pablo Saraza-Canflanca, Héctor Carrasco-Lopez, Piedad Brox, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
Improving the reliability of SRAM-based PUFs in the presence of aging. DTIS 2020: 1-6
2010 – 2019
- 2019
- [j18]Javier Diaz-Fortuny, Javier Martín-Martínez, Rosana Rodríguez, Rafael Castro-López, Elisenda Roca, Xavier Aragonès, Enrique Barajas, Diego Mateo, Francisco V. Fernández, Montserrat Nafría:
A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI. IEEE J. Solid State Circuits 54(2): 476-488 (2019) - [j17]Fábio Passos, Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández:
A two-step surrogate modeling strategy for single-objective and multi-objective optimization of radiofrequency circuits. Soft Comput. 23(13): 4911-4925 (2019) - [j16]Ricardo Martins, Nuno Lourenço, Fábio Passos, Ricardo Povoa, António Canelas, Elisenda Roca, Rafael Castro-López, Javier J. Sieiro, Francisco V. Fernández, Nuno Horta:
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 989-1002 (2019) - [c46]Antonio Toro-Frías, Pablo Saraza-Canflanca, Fábio Passos, Pablo Martín-Lloret, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández:
Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator. DATE 2019: 78-83 - [c45]Pablo Saraza-Canflanca, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca Moreno, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández:
New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors. DATE 2019: 150-155 - [c44]G. Pedreira, Javier Martín-Martínez, Javier Diaz-Fortuny, Pablo Saraza-Canflanca, Rosana Rodríguez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Montserrat Nafría:
A New Time Efficient Methodology for the Massive Characterization of RTN in CMOS Devices. IRPS 2019: 1-5 - [c43]Fábio Passos, Elisenda Roca, Rafael Castro-López, Nuno Horta, Francisco V. Fernández:
Synthesis of mm-Wave circuits using-EM-simulated passive structure libraries. SMACD 2019: 57-60 - [c42]Pablo Saraza-Canflanca, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández:
TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level. SMACD 2019: 197-200 - [c41]Juan Núñez, Elisenda Roca, Rafael Castro-López, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández:
Experimental Characterization of Time-Dependent Variability in Ring Oscillators. SMACD 2019: 229-232 - [c40]Pablo Martín-Lloret, Juan Núñez, Elisenda Roca, Rafael Castro-López, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández:
An IC Array for the Statistical Characterization of Time-Dependent Variability of Basic Circuit Blocks. SMACD 2019: 241-244 - 2018
- [j15]Saiyd Ahyoune, Javier J. Sieiro, Tomás Carrasco Carrillo, Neus Vidal, José María López-Villegas, Elisenda Roca, Francisco V. Fernández:
Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator. Integr. 63: 332-341 (2018) - [j14]Fábio Passos, Ricardo Martins, Nuno Lourenço, Elisenda Roca, Ricardo Povoa, António Canelas, Rafael Castro-López, Nuno Horta, Francisco V. Fernández:
Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology. Integr. 63: 351-361 (2018) - [j13]Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández:
A Comparison of Automated RF Circuit Design Methodologies: Online Versus Offline Passive Component Design. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2386-2394 (2018) - [c39]Javier Diaz-Fortuny, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
CMOS Characterization and Compact Modelling for Circuit Reliability Simulation. IOLTS 2018: 139-142 - [c38]Victor M. van Santen, Javier Diaz-Fortuny, Hussam Amrouch, Javier Martín-Martínez, Rosana Rodríguez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Jörg Henkel, Montserrat Nafría:
Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability. IRPS 2018: 6-1 - [c37]Enrique Barajas, Xavier Aragonès, Diego Mateo, Francesc Moll, Antonio Rubio, Javier Martín-Martínez, Rosana Rodríguez, Marc Porti, Montserrat Nafría, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
Analysis of Body Bias and RTN-Induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI Technology. PATMOS 2018: 82-87 - [c36]Fábio Passos, Ricardo Martins, Nuno C. Lourenço, Elisenda Roca, Rafael Castro-López, Ricardo Povoa, António Canelas, Nuno Horta, Francisco V. Fernández:
Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs. SMACD 2018: 1-164 - [c35]Antonio Toro-Frías, Pablo Martín-Lloret, Javier Martín-Martínez, Rafael Castro-López, Elisenda Roca, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández:
Lifetime Calculation Using a Stochastic Reliability Simulator for Analog ICs. SMACD 2018: 1-9 - [c34]Pablo Saraza-Canflanca, Javier Diaz-Fortuny, Antonio Toro-Frías, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández:
Automated Massive RTN Characterization Using a Transistor Array Chip. SMACD 2018: 29-32 - [c33]Javier Diaz-Fortuny, Pablo Saraza-Canflanca, Antonio Toro-Frías, Rafael Castro-López, Javier Martín-Martínez, Elisenda Roca, Rosana Rodríguez, Francisco V. Fernández, Montserrat Nafría:
A Model Parameter Extraction Methodology Including Time-Dependent Variability for Circuit Reliability Simulation. SMACD 2018: 53-56 - [c32]Pablo Saraza-Canflanca, D. Malagon, Fábio Passos, A. Toro, Juan Núñez, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández:
Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models. SMACD 2018: 73-76 - 2017
- [j12]Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández:
Radio-frequency inductor synthesis using evolutionary computation and Gaussian-process surrogate modeling. Appl. Soft Comput. 60: 495-507 (2017) - [j11]Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández:
An inductor modeling and optimization toolbox for RF circuit design. Integr. 58: 463-472 (2017) - [j10]Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Javier J. Sieiro, José María López-Villegas, Neus Vidal:
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(1): 15-26 (2017) - [c31]Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández:
An algorithm for a class of real-life multi-objective optimization problems with a sweeping objective. CEC 2017: 734-740 - [c30]Pablo Martín-Lloret, Antonio Toro-Frías, Javier Martín-Martínez, Rafael Castro-López, Elisenda Roca, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández:
A size-adaptive time-step algorithm for accurate simulation of aging in analog ICs. ISCAS 2017: 1-4 - [c29]Saiyd Ahyoune, Javier J. Sieiro, Tomás Carrasco Carrillo, Neus Vidal, José María López-Villegas, Elisenda Roca, Francisco V. Fernández:
Extending the frequency range of quasi-static electromagnetic solvers. SMACD 2017: 1-4 - [c28]Javier Diaz-Fortuny, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
TARS: A toolbox for statistical reliability modeling of CMOS devices. SMACD 2017: 1-4 - [c27]Javier Diaz-Fortuny, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Enrique Barajas, Xavier Aragonès, Diego Mateo:
A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging. SMACD 2017: 1-4 - [c26]Nuno C. Lourenço, Ricardo Martins, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization. SMACD 2017: 1-4 - [c25]Pablo Martín-Lloret, Antonio Toro-Frías, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría:
CASE: A reliability simulation tool for analog ICs. SMACD 2017: 1-4 - [c24]Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks. SMACD 2017: 1-4 - [c23]Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno C. G. Horta:
Systematic design of a voltage controlled oscillator using a layout-aware approach. SMACD 2017: 1-4 - [c22]Antonio Toro-Frías, Pablo Martín-Lloret, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría:
Including a stochastic model of aging in a reliability simulation flow. SMACD 2017: 1-4 - 2016
- [j9]Elisenda Roca, Javier J. Sieiro:
Introduction to the special issue on Radio Frequency Integrated Circuits (RFIC) design techniques. Integr. 52: 183-184 (2016) - [j8]Antonio Toro-Frías, Pablo Martín-Lloret, Javier Martín-Martínez, Rafael Castro-López, Elisenda Roca, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández:
Reliability simulation for analog ICs: Goals, solutions, and challenges. Integr. 55: 341-348 (2016) - [c21]Fábio Passos, Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández:
Accurate synthesis of integrated RF passive components using surrogate models. DATE 2016: 397-402 - [c20]Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández:
SIDe-O: A toolbox for surrogate inductor design and optimization. SMACD 2016: 1-4 - [c19]Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Y. Ye, Domenico Spina, Tom Dhaene:
Frequency-dependent parameterized macromodeling of integrated inductors. SMACD 2016: 1-4 - 2015
- [c18]Fábio Passos, Mouna Kotti, Reinier Gonzalez-Echevarria, M. Helena Fino, Mourad Fakhfakh, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández:
Physical vs. surrogate models of passive RF devices. ISCAS 2015: 117-120 - [c17]Manuel Velasco-Jimenez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
Design space exploration using hierarchical composition of performance models. ISCAS 2015: 1941-1944 - 2014
- [j7]Reinier Gonzalez-Echevarria, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Javier J. Sieiro, Neus Vidal, José María López-Villegas:
Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(8): 1269-1273 (2014) - [c16]Manuel Velasco-Jimenez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
Implementation issues in the hierarchical composition of performance models of analog circuits. DATE 2014: 1-6 - [c15]Fábio Passos, Maria Helena Fino, Elisenda Roca:
Single-Objective Optimization Methodology for the Design of RF Integrated Inductors. DoCEIS 2014: 569-574 - 2013
- [c14]Fábio Passos, M. Helena Fino, Elisenda Roca:
A wideband lumped-element model for arbitrarily shaped integrated inductors. ECCTD 2013: 1-4 - [c13]Fábio Passos, M. Helena Fino, Elisenda Roca Moreno:
Analythical characterization of variable width integrated spiral inductors. MIXDES 2013: 586-591 - 2011
- [c12]Antonio Toro-Frías, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
Layout-aware Pareto fronts of electronic circuits. ECCTD 2011: 345-348 - 2010
- [c11]Francisco V. Fernández, Juan Esteban-Muller, Elisenda Roca, Rafael Castro-López:
Stopping criteria in evolutionary algorithms for multi-objective performance optimization of integrated inductors. IEEE Congress on Evolutionary Computation 2010: 1-8
2000 – 2009
- 2009
- [j6]Bo Liu, Francisco V. Fernández, Georges G. E. Gielen, Rafael Castro-López, Elisenda Roca:
A memetic approach to the automatic design of high-performance analog integrated circuits. ACM Trans. Design Autom. Electr. Syst. 14(3): 42:1-42:24 (2009) - [c10]Sonia Vargas-Sierra, Elisenda Roca, Gustavo Liñán Cembrano:
APS design alternatives in 0.18μm CMOS image sensor technology. ECCTD 2009: 1-4 - [c9]Gustavo Liñán Cembrano, Luis Carranza, Betsaida Alexandre, Elisenda Roca, Ángel Rodríguez-Vázquez:
A focal plane processor for continuous-time 1-D optical correlation applications. ECCTD 2009: 173-176 - [c8]Elisenda Roca, Rafael Castro-López, Francisco V. Fernández:
Hierarchical synthesis based on pareto-optimal fronts. ECCTD 2009: 755-758 - [c7]Elisenda Roca, Mourad Fakhfakh, Rafael Castro-López, Francisco V. Fernández:
Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview. ICECS 2009: 251-254 - 2008
- [j5]Rafael Castro-López, Oscar Guerra, Elisenda Roca, Francisco V. Fernández:
An Integrated Layout-Synthesis Approach for Analog ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1179-1189 (2008) - 2006
- [c6]L. Carranza, R. Laviana, Sonia Vargas-Sierra, Jorge Cuadri, Gustavo Liñán, Elisenda Roca, Ángel Rodríguez-Vázquez:
Locust-inspired vision system on chip architecture for collision detection in automotive applications. ISCAS 2006 - [c5]Rocío Maldonado-López, Fernando Vidal-Verdú, Gustavo Lilian, Elisenda Roca, Ángel Rodríguez-Vázquez:
Tactile Retina for Slip Detection. VECIMS 2006: 96-101 - 2004
- [j4]Ángel Rodríguez-Vázquez, Gustavo Liñán Cembrano, L. Carranza, Elisenda Roca Moreno, Ricardo Carmona-Galán, Francisco Jiménez-Garrido, Rafael Domínguez-Castro, Servando Espejo-Meana:
ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(5): 851-863 (2004) - 2000
- [c4]Oscar Guerra, Elisenda Roca, Francisco V. Fernández, Ángel Rodríguez-Vázquez:
A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits. DATE 2000: 48-52 - [c3]Oscar Guerra, Juan D. Rodríguez-García, Elisenda Roca, Francisco V. Fernández, Ángel Rodríguez-Vázquez:
An error-controlled methodology for approximate hierarchical symbolic analysis. ISCAS 2000: 133-136
1990 – 1999
- 1999
- [j3]Ángel Rodríguez-Vázquez, Elisenda Roca, Manuel Delgado-Restituto, Servando Espejo-Meana, Rafael Domínguez-Castro:
MOST-Based Design and Scaling of Synaptic Interconnections in VLSI Analog Array Processing CNN Chips. J. VLSI Signal Process. 23(2-3): 239-266 (1999) - [j2]Elisenda Roca, Servando Espejo-Meana, Rafael Domínguez-Castro, Gustavo Liñán, Ángel Rodríguez-Vázquez:
A Programmable Imager for Very High Speed Cellular Signal Processing. J. VLSI Signal Process. 23(2-3): 305-318 (1999) - [c2]Oscar Guerra, Juan D. Rodríguez-García, Elisenda Roca, Francisco V. Fernández, Ángel Rodríguez-Vázquez:
An Accurate Error Control Mechanism for Simplification Before Generation Algorihms. DATE 1999: 412- - 1998
- [j1]Elisenda Roca, Fabián Frutos, Servando Espejo-Meana, Rafael Domínguez-Castro, Ángel Rodríguez-Vázquez:
Electrooptical measurement system for the DC characterization of visible detectors for CMOS-compatible vision chips. IEEE Trans. Instrum. Meas. 47(2): 499-506 (1998) - [c1]Oscar Guerra, Juan D. Rodríguez-García, Elisenda Roca, Francisco V. Fernández, Ángel Rodríguez-Vázquez:
A simplification before and during generation methodology for symbolic large-circuit analysis. ICECS 1998: 81-84
Coauthor Index
[c63] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [j26] [j25] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [j24] [j23] [j22] [j21] [j20] [j19] [c47] [j18] [j17] [j16] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [j14] [j13] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [j12] [j11] [j10] [c31] [c30] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [j8] [c21] [c20] [c19] [c18] [c17] [j7] [c16] [c12] [c11] [j6] [c8] [c7] [j5]
[c63] [c61] [c60] [c59] [c58] [c57] [c56] [j26] [j25] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [j24] [j23] [j22] [j21] [j20] [j19] [c47] [j18] [j17] [j16] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [j15] [j14] [j13] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [j12] [j11] [j10] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [j8] [c21] [c20] [c19] [c18] [c17] [j7] [c16] [c12] [c11] [j6] [c8] [c7] [j5] [c4] [c3] [c2] [c1]
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To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
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Archived links via Wayback Machine
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load citations from opencitations.net
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OpenAlex data
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last updated on 2024-08-05 20:20 CEST by the dblp team
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