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2020 – today
- 2023
[c12]Wen-Chieh Chen
, S.-H. Chen, Anabela Veloso, Kateryna Serbulova, Geert Hellings, Guido Groeseneken:
Upcoming Challenges of ESD Reliability in DTCO with BS-PDN Routing via BPRs. VLSI Technology and Circuits 2023: 1-2- [c11]S. Yang, Pieter Schuddinck, Marie Garcia Bardon, Yang Xiang, Anabela Veloso, B. T. Chan, Gioele Mirabelli, Gaspard Hiblot, Geert Hellings, Julien Ryckaert:
PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c10]Anabela Veloso, Geert Eneman, An De Keersgieter, P. Favia, Andriy Hikavyy, Rongmei Chen, Anne Jourdain, N. Horiguchi:
Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling. ICICDT 2022: 51-54 - [c9]Anabela Veloso, Anne Jourdain, D. Radisic, Rongmei Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Yusuke Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi:
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. VLSI Technology and Circuits 2022: 284-285 - [c8]Rongmei Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, Anabela Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne:
Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. VLSI Technology and Circuits 2022: 429-430 - [c7]Kateryna Serbulova, S.-H. Chen, Geert Hellings, Anabela Veloso, Anne Jourdain, Dimitri Linten, Jo De Boeck, Guido Groeseneken, Julien Ryckaert, Geert Van der Plas, Eric Beyne, Eugenio Dentoni Litta, Naoto Horiguchi:
Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO. VLSI Technology and Circuits 2022: 431-432 - 2021
- [j4]Carlos H. S. Coelho, João Antonio Martino, Marcello Bellodi, Eddy Simoen, Anabela Veloso, Paula Ghedini Der Agopian:
Analysis of zero-temperature coefficient behavior on vertically stacked double nanosheet nMOS devices. Microelectron. J. 117: 105277 (2021)
2010 – 2019
- 2019
- [c6]Eddy Simoen, Alberto Vinicius Oliveira, Anabela Veloso, Adrian Vaisman Chasin, Romain Ritzenthaler, Hans Mertens, Naoto Horiguchi, Cor Claeys:
Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors. ASICON 2019: 1-4 - [c5]Trong Huynh Bao, Anabela Veloso, Sushil Sakhare, Philippe Matagne, Julien Ryckaert, Manu Perumkunnil, Davide Crotti, Farrukh Yasin, Alessio Spessot, Arnaud Furnémont, Gouri Sankar Kar, Anda Mocuta:
Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications. DAC 2019: 13 - 2018
- [c4]Bertrand Parvais, Geert Hellings, Marko Simicic, Pieter Weckx, Jérôme Mitard, Doyoung Jang, V. Deshpande, B. van Liempc, Anabela Veloso, A. Vandooren, Niamh Waldron, Piet Wambacq, Nadine Collaert, Diederik Verkest:
Scaling CMOS beyond Si FinFET: an analog/RF perspective. ESSDERC 2018: 158-161 - 2016
- [c3]Nadine Collaert, AliReza Alian, Hiroaki Arimura, Geert Boccardi, Geert Eneman, Jacopo Franco, Tsvetan Ivanov, Dennis Lin, Jérôme Mitard, S. Ramesh, R. Rooyackers, Marc Schaekers, A. Sibaya-Hernandez, S. Sioncke, Quentin Smets, Abhitosh Vais, A. Vandooren, Anabela Veloso, Anne S. Verhulst, Devin Verreck, Niamh Waldron, Amey Walke, Liesbeth Witters, H. Yu, X. Zhou, Aaron Voon-Yew Thean:
Beyond-Si materials and devices for more Moore and more than Moore applications. ICICDT 2016: 1-5 - 2014
- [c2]Trong Huynh Bao, Dmitry Yakimets, Julien Ryckaert, Ivan Ciofi, Rogier Baert, Anabela Veloso, Jürgen Bömmels, Nadine Collaert, Philippe Roussel, S. Demuynck, Praveen Raghavan, Abdelkarim Mercha, Zsolt Tokei, Diederik Verkest, Aaron Thean, Piet Wambacq:
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. ESSDERC 2014: 102-105 - 2012
- [c1]Eddy Simoen, Marc Aoulaiche, Anabela Veloso, M. Jurczak, Cor Claeys, L. Mendes Almeida, Maria Glória Caño de Andrade, A. Luque Rodriguez, J. A. Jimenez Tejada, Christian Caillat, Pierre Fazan:
On the correlation between the retention time of FBRAM and the low-frequency noise of UTBOX SOI nMOSFETs. ESSDERC 2012: 338-341
2000 – 2009
- 2007
- [j3]A. Shickova, Ben Kaczer, Anabela Veloso, Marc Aoulaiche, M. Houssa, Herman E. Maes, Guido Groeseneken, J. A. Kittl:
NBTI reliability of Ni FUSI/HfSiON gates: Effect of silicide phase. Microelectron. Reliab. 47(4-5): 505-507 (2007) - [j2]A. Kerber, Luigi Pantisano, Anabela Veloso, Guido Groeseneken, Martin Kerber:
Reliability screening of high-k dielectrics based on voltage ramp stress. Microelectron. Reliab. 47(4-5): 513-517 (2007) - [j1]A. Rothschild, R. Mitsuhashi, Christoph Kerner, X. Shi, J. L. Everaert, L. Date, Thierry Conard, Olivier Richard, C. Vrancken, R. Verbeeck, Anabela Veloso, A. Lauwers, Muriel de Potter de ten Broeck, I. Debusschere, M. Jurczak, M. Niwa, Philippe Absil, S. Biesemans:
Optimization of HfSiON using a design of experiment (DOE) approach on 0.45 V Vt Ni-FUSI CMOS transistors. Microelectron. Reliab. 47(4-5): 521-524 (2007)
Coauthor Index
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