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N. Sudha
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- affiliation: Nanyang Technological University, Singapore
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2010 – 2019
- 2016
- [j18]Tahiyah Nou Shene, K. Sridharan, N. Sudha:
Real-Time SURF-Based Video Stabilization System for an FPGA-Driven Mobile Robot. IEEE Trans. Ind. Electron. 63(8): 5012-5021 (2016) - 2015
- [c18]N. Sudha:
Multicore processor - Architecture and programming. VDAT 2015: 1-2 - [c17]N. Sudha, D. Bharat Chandrahas:
A pipelined memory-efficient architecture for face detection and tracking on a multicore environment. VDAT 2015: 1-2 - 2014
- [c16]Natarajan Sudha, K. Sridharan, Dan Wilkinson:
A pipelined architecture for motion tracking on a multicore environment. ISIC 2014: 384-387 - 2013
- [j17]Natarajan Sudha, Niladri B. Puhan, Pramod Kumar Meher:
Special section on image and video processing for security. Signal Image Video Process. 7(4): 607-608 (2013) - 2012
- [j16]Pravin Kakar, N. Sudha:
Exposing Postprocessed Copy-Paste Forgeries Through Transform-Invariant Features. IEEE Trans. Inf. Forensics Secur. 7(3): 1018-1028 (2012) - [j15]Pravin Kakar, N. Sudha:
Verifying Temporal Data in Geotagged Images Via Sun Azimuth Estimation. IEEE Trans. Inf. Forensics Secur. 7(3): 1029-1039 (2012) - [c15]Pravin Kakar, Natarajan Sudha:
Authenticating Image Metadata Elements Using Geolocation Information and Sun Direction Estimation. ICME 2012: 236-241 - 2011
- [j14]Niladri B. Puhan, Natarajan Sudha:
Coarse indexing of iris database based on iris colour. Int. J. Biom. 3(4): 353-375 (2011) - [j13]Niladri B. Puhan, Natarajan Sudha, Anirudh Sivaraman Kaushalram:
Efficient segmentation technique for noisy frontal view iris images using Fourier spectral density. Signal Image Video Process. 5(1): 105-119 (2011) - [j12]Natarajan Sudha, A. R. Mohan, Pramod Kumar Meher:
A Self-Configurable Systolic Architecture for Face Recognition System Based on Principal Component Neural Network. IEEE Trans. Circuits Syst. Video Technol. 21(8): 1071-1084 (2011) - [j11]N. Sudha, A. R. Mohan:
Hardware-Efficient Image-Based Robotic Path Planning in a Dynamic Environment and Its FPGA Implementation. IEEE Trans. Ind. Electron. 58(5): 1907-1920 (2011) - [j10]Pravin Kakar, Natarajan Sudha, Wee Ser:
Exposing Digital Image Forgeries by Detecting Discrepancies in Motion Blur. IEEE Trans. Multim. 13(3): 443-452 (2011) - 2010
- [j9]Fahad Hameed Ahmad, N. Sudha:
Multi-modal Medical Images Registration Using Differential Geometry and the Hausdorff Distance. J. Intell. Syst. 19(4): 363-377 (2010) - [c14]Pravin Kakar, Natarajan Sudha, Wee Ser:
Detecting digital image forgeries through inconsistent motion blur. ICME 2010: 486-491 - [c13]Fahad Hameed Ahmad, Natarajan Sudha, Jimmy Jiang Liu:
Feature Based Non-rigid Registration Using Quaternion Subdivision. ICMB 2010: 373-382
2000 – 2009
- 2008
- [j8]N. Sudha, A. R. Mohan:
Design of a hardware accelerator for path planning on the Euclidean distance transform. J. Syst. Archit. 54(1-2): 253-264 (2008) - 2007
- [j7]E. P. Vivek, N. Sudha:
Robust Hausdorff distance measure for face recognition. Pattern Recognit. 40(2): 431-442 (2007) - [c12]Natarajan Sudha:
A Hardware Accelerator for Path Planning on a Distance Transform. CCA 2007: 409-414 - [c11]Natarajan Sudha, Yung Ho Kenny Wong:
Hausdorff Distance for Iris Recognition. ISIC 2007: 614-619 - [c10]N. Sudha, Niladri B. Puhan, Hua Xia, Xudong Jiang:
Local Partial Hausdorff Distance Measure Based on Binary Feature for Iris Recognition. IICAI 2007: 621-629 - 2006
- [j6]E. P. Vivek, N. Sudha:
Gray Hausdorff distance measure for comparing face images. IEEE Trans. Inf. Forensics Secur. 1(3): 342-349 (2006) - 2005
- [j5]N. Sudha:
A pipelined array architecture for Euclidean distance transformation and its FPGA implementation. Microprocess. Microsystems 29(8-9): 405-410 (2005) - [c9]N. Sudha, E. P. Vivek:
A High-Speed VLSI Array Architecture for Euclidean Metric-Based Hausdorff Distance Measures Between Images. HiPC 2005: 180-189 - [c8]E. P. Vivek, N. Sudha:
Gray Hausdorff Distance Measures for Comparing Face Images. IICAI 2005: 3103-3114 - [c7]Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti:
A Principal Component Neural Network-Based Face Recognition System and Its ASIC Implementation. VLSI Design 2005: 795-798 - 2004
- [j4]N. Sudha:
An ASIC implementation of Kohonen's map based colour image compression. Real Time Imaging 10(1): 31-39 (2004) - [j3]Natarajan Sudha, K. Sridharan:
A high-speed VLSI design and ASIC implementation for constructing Euclidean distance-based discrete Voronoi diagram. IEEE Trans. Robotics Autom. 20(2): 352-358 (2004) - [c6]Chakka Siva Sai Prasanna, N. Sudha, V. Kamakoti:
A Hardware-Directed Face Recognition System Based on Local Eigen-analysis with PCNN. ICONIP 2004: 327-332 - [c5]R. Suguna, N. Sudha, C. Chandra Sekhar:
A Fast and Efficient Face Detection Technique Using Support Vector Machine. ICONIP 2004: 338-343 - [c4]N. Sudha:
An ASIC Implementation of Kohonen's Map Based Color Image Compression. VLSI Design 2004: 677-680 - [c3]N. Sudha:
An Area-Efficient Pipelined Array Architecture for Euclidean Distance Transformation and Its FPGA Implementation. VLSI Design 2004: 689-692 - 2003
- [j2]N. Sudha, Thambipillai Srikanthan, Babu Mailachalam:
A VLSI architecture for 3-D self-organizing map based color quantization and its FPGA implementation. J. Syst. Archit. 48(11-12): 337-352 (2003) - [j1]N. Sudha:
Design of a Cellular Architecture for Fast Computation of the Skeleton. J. VLSI Signal Process. 35(1): 61-73 (2003)
1990 – 1999
- 1999
- [c2]N. Sudha, Sukumar Nandi, K. Sridharan:
A Parallel Algorithm to Construct Voronoi Diagram and Its VLSI Architecture. ICRA 1999: 1683-1688 - 1998
- [c1]N. Sudha, Sukumar Nandi:
A parallel skeletonization algorithm and its VLSI architecture. HiPC 1998: 65-72
Coauthor Index
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