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ORCIDNevine Nassif
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2020 – today
- 2024
[c6]Ashley O. Munch, Nevine Nassif, Carleton L. Molnar, Jason Crop, Rich Gammack, Chinmay P. Joshi, Goran Zelic, Kambiz Munshi, Min Huang, Charles Morganti, Sireesha Kandula, Arijit Biswas:
2.3 Emerald Rapids: 5th-Generation Intel® Xeon® Scalable Processors. ISSCC 2024: 40-42- 2022
- [c5]Nevine Nassif, Ashley O. Munch, Carleton L. Molnar, Gerald Pasdast, Sitaraman V. Lyer, Zibing Yang, Oscar Mendoza, Mark Huddart, Srikrishnan Venkataraman, Sireesha Kandula, Rafi Marom, Alexandra M. Kern, William J. Bowhill, David R. Mulvihill, Srikanth Nimmagadda, Varma Kalidindi, Jonathan Krause, Mohammad M. Haq, Roopali Sharma, Kevin Duda:
Sapphire Rapids: The Next-Generation Intel Xeon Scalable Processor. ISSCC 2022: 44-46
2010 – 2019
- 2016
- [j1]William J. Bowhill, Blaine A. Stackhouse, Nevine Nassif, Zibing Yang, Arvind Raghavan, Oscar Mendoza, Charles Morganti, Chris Houghton, Dan Krueger, Olivier Franza, Jayen Desai, Jason Crop, Brian Brock, Dave Bradley, Chris Bostak, Sal Bhimji, Matt Becker:
The Xeon® Processor E5-2600 v3: a 22 nm 18-Core Product Family. IEEE J. Solid State Circuits 51(1): 92-104 (2016) - 2015
- [c4]William J. Bowhill, Blaine A. Stackhouse, Nevine Nassif, Zibing Yang, Arvind Raghavan, Charles Morganti, Chris Houghton, Dan Krueger, Olivier Franza, Jayen Desai, Jason Crop, Dave Bradley, Chris Bostak, Sal Bhimji, Matt Becker:
4.5 The Xeon® processor E5-2600 v3: A 22nm 18-core product family. ISSCC 2015: 1-3
1990 – 1999
- 1998
- [c3]Nevine Nassif, Madhav P. Desai, Dale H. Hall:
Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor. DAC 1998: 230-235 - [c2]Emily J. Shriver, Dale H. Hall, Nevine Nassif, Nadir E. Rahman, Nick L. Rethman, Gill Watt, Jim A. Farrell:
Timing verification of the 21264: A 600 MHz full-custom microprocessor. ICCD 1998: 96-103 - [c1]Joel Grodstein, Nick Rethman, Nevine Nassif:
Static race verification for networks with reconvergent clocks. ICCD 1998: 524-529
Coauthor Index
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