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ORCIDAmr Elshazly
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2010 – 2019
- 2019
[j22]Jihwan Kim
, Ajay Balankutty, Rajeev K. Dokania, Amr Elshazly, Hyung Seok Kim, Sandipan Kundu, Dan Shi, Skyler Weaver, Kai Yu, Frank O'Mahony:
A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET. IEEE J. Solid State Circuits 54(1): 29-42 (2019)- 2018
- [j21]Ahmed Elkholy, Saurabh Saxena, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu:
Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers. IEEE J. Solid State Circuits 53(6): 1806-1817 (2018) - [j20]Kuan-Yueh James Shen, Syed Feruz Syed Farooq, Yongping Fan, Khoa Minh Nguyen, Qi Wang, Mark Neidengard, Nasser A. Kurd, Amr Elshazly:
A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(7): 2109-2117 (2018) - [c25]Jihwan Kim, Ajay Balankutty, Rajeev K. Dokania, Amr Elshazly, Hyung Seok Kim, Sandipan Kundu, Skyler Weaver, Kai Yu, Frank O'Mahony:
A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS. ISSCC 2018: 102-104 - 2017
- [j19]Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu:
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. IEEE J. Solid State Circuits 52(9): 2306-2320 (2017) - [j18]Romesh Kumar Nandwana, Saurabh Saxena, Amr Elshazly, Kartikeya Mayaram, Pavan Kumar Hanumolu:
A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(2): 283-295 (2017) - 2016
- [j17]Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu:
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition. IEEE J. Solid State Circuits 51(2): 428-439 (2016) - [j16]Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu:
A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider. IEEE J. Solid State Circuits 51(8): 1771-1784 (2016) - [c24]Kuan-Yueh James Shen, Syed Feruz Syed Farooq, Yongping Fan, Khoa Minh Nguyen, Qi Wang, Amr Elshazly, Nasser A. Kurd:
19.4 A 0.17-to-3.5mW 0.15-to-5GHz SoC PLL with 15dB built-in supply noise rejection and self-bandwidth control in 14nm CMOS. ISSCC 2016: 330-331 - 2015
- [j15]Woo-Seok Choi, Tejasvi Anand, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu:
A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links. IEEE J. Solid State Circuits 50(3): 737-748 (2015) - [j14]Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu:
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC. IEEE J. Solid State Circuits 50(4): 867-881 (2015) - [j13]Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu:
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. IEEE J. Solid State Circuits 50(4): 882-895 (2015) - [j12]Seong Joong Kim, Qadeer Khan, Mrunmay Talegaonkar, Amr Elshazly, Arun Rao, Nathanael Griesert, Greg Winter, William McIntyre, Pavan Kumar Hanumolu:
High Frequency Buck Converter Design Using Time-Based Control Techniques. IEEE J. Solid State Circuits 50(4): 990-1001 (2015) - [j11]Tejasvi Anand, Mrunmay Talegaonkar, Ahmed Elkholy, Saurabh Saxena, Amr Elshazly, Pavan Kumar Hanumolu:
A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links. IEEE J. Solid State Circuits 50(12): 3101-3119 (2015) - [c23]Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu:
A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter. CICC 2015: 1-4 - [c22]Tejasvi Anand, Mrunmay Talegaonkar, Ahmed Elkholy, Saurabh Saxena, Amr Elshazly, Pavan Kumar Hanumolu:
3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS. ISSCC 2015: 1-3 - [c21]Jihwan Kim, Ajay Balankutty, Amr Elshazly, Yan-Yu Huang, Hang Song, Kai Yu, Frank O'Mahony:
3.5 A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS. ISSCC 2015: 1-3 - 2014
- [j10]Guanghua Shu, Saurabh Saxena, Woo-Seok Choi, Mrunmay Talegaonkar, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu:
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop. IEEE J. Solid State Circuits 49(4): 1036-1047 (2014) - [j9]Amr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu:
A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators - Analysis, Design, and Measurement Techniques. IEEE J. Solid State Circuits 49(5): 1184-1197 (2014) - [j8]Mrunmay Talegaonkar, Amr Elshazly, Karthikeyan Reddy, Praveen Prabha, Tejasvi Anand, Pavan Kumar Hanumolu:
An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS. IEEE J. Solid State Circuits 49(10): 2228-2242 (2014) - [j7]Tejasvi Anand, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu:
A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links. IEEE J. Solid State Circuits 49(10): 2243-2258 (2014) - [c20]Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Tejasvi Anand, Amr Elshazly, Pavan Kumar Hanumolu:
8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. ISSCC 2014: 150-151 - [c19]Ahmed Elkholy, Amr Elshazly, Saurabh Saxena, Guanghua Shu, Pavan Kumar Hanumolu:
15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS. ISSCC 2014: 272-273 - [c18]Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu:
A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC. VLSIC 2014: 1-2 - [c17]Amr Elshazly, Ajay Balankutty, Yan-Yu Huang, Kai Yu, Frank O'Mahony:
A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS. VLSIC 2014: 1-2 - [c16]Qadeer Ahmad Khan, Seong Joong Kim, Mrunmay Talegaonkar, Amr Elshazly, Arun Rao, Nathanael Griesert, Greg Winter, William McIntyre, Pavan Kumar Hanumolu:
A 10-25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW. VLSIC 2014: 1-2 - [c15]Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu:
A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. VLSIC 2014: 1-2 - [c14]Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu:
A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. VLSIC 2014: 1-2 - [c13]Brian Young, Karthik Reddy, Sachin Rao, Amr Elshazly, Tejasvi Anand, Pavan Kumar Hanumolu:
A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators. VLSIC 2014: 1-2 - 2013
- [j6]Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu:
Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops. IEEE J. Solid State Circuits 48(6): 1416-1428 (2013) - [c12]Tejasvi Anand, Mrunmay Talegaonkar, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu:
A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time. ISSCC 2013: 256-257 - 2012
- [j5]Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu:
A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer. IEEE J. Solid State Circuits 47(12): 2916-2927 (2012) - [c11]Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu:
A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer. ISSCC 2012: 152-154 - [c10]Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu:
A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC. ISSCC 2012: 242-244 - [c9]Amr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu:
A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators. ISSCC 2012: 464-466 - [c8]Qadeer Khan, Amr Elshazly, Sachin Rao, Rajesh Inti, Pavan Kumar Hanumolu:
A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control. VLSIC 2012: 182-183 - [c7]Amr Elshazly, Rajesh Inti, Mrunmay Talegaonkar, Pavan Kumar Hanumolu:
A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity. VLSIC 2012: 188-189 - 2011
- [j4]Wenjing Yin, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu:
A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking. IEEE J. Solid State Circuits 46(8): 1870-1880 (2011) - [j3]Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu:
A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration. IEEE J. Solid State Circuits 46(12): 2759-2771 (2011) - [j2]Rajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu:
A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance. IEEE J. Solid State Circuits 46(12): 3150-3162 (2011) - [j1]Wenjing Yin, Rajesh Inti, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu:
A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery. IEEE J. Solid State Circuits 46(12): 3163-3173 (2011) - [c6]Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu:
A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration. ISSCC 2011: 92-94 - [c5]Rajesh Inti, Amr Elshazly, Brian Young, Wenjing Yin, Marcel A. Kossel, Thomas Toifl, Pavan Kumar Hanumolu:
A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS. ISSCC 2011: 152-154 - [c4]Rajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu:
A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance. ISSCC 2011: 438-450 - [c3]Wenjing Yin, Rajesh Inti, Amr Elshazly, Pavan Kumar Hanumolu:
A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery. ISSCC 2011: 440-442 - 2010
- [c2]Brian Young, Sunwoo Kwon, Amr Elshazly, Pavan Kumar Hanumolu:
A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth. CICC 2010: 1-4
2000 – 2009
- 2006
- [c1]Amr Elshazly, Khaled M. Sharaf:
2 GHz 1V sub-mW, fully integrated PLL for clock recovery applications using self-skewing. ISCAS 2006
Coauthor Index
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